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ST72260Gx, ST72262Gx, ST72264Gx
8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

Memories - 4 K or 8 Kbytes Program memory: ROM or Single voltage extended Flash (XFlash) with read-out protection write protection and InCircuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55C. - 256 bytes RAM Clock, Reset and Supply Management - Enhanced reset system - Enhanced low voltage supply supervisor (LVD) with 3 programmable levels and auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures - Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock - PLL for 2x frequency multiplication - Clock-out capability - 4 Power Saving Modes: Halt, Active Halt,Wait and Slow Interrupt Management - Nested interrupt controller - 10 interrupt vectors plus TRAP and RESET - 22 external interrupt lines (on 2 vectors) 22 I/O Ports - 22 multifunctional bidirectional I/O lines - 20 alternate function lines - 8 high sink outputs 4 Timers - Main Clock Controller with Real time base and Clock-out capabilities - Configurable watchdog timer
SDIP32
LFBGA 6x6mm
SO28

- Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes 3 Communication Interfaces - SPI synchronous serial interface - I2C multimaster interface (SMBus V1.1 Compliant) - SCI asynchronous serial interface 1 Analog peripheral - 10-bit ADC with 6 input channels Instruction Set - 8-bit data manipulation - 63 basic instructions with illegal opcode detection - 17 main addressing modes - 8 x 8 unsigned multiply instruction Development Tools - Full hardware/software development package
Device Summary
Features Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages
ST72260G1
4K Watchdog timer, RTC, Two16-bit timers, SPI
ST72262G1 ST72262G2 ST72264G1
4K 8K 4K
ST72264G2
8K 256 (128) Watchdog timer, RTC, Watchdog timer, RTC, Two 16-bit timers, SPI, ADC Two 16-bit timers, SPI, SCI, I2C, ADC 2.7 V to 5.5 V Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 MHz 0 C to +70 C / -40 C to +85 C -40 C to +85 C -40 C to +85 C SO28 / SDIP32 SO28 / SDIP32 LFBGA
Rev. 3
June 2005 1/172
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 4.3 4.4 4.5 4.6 4.7 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 5.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 6.3 6.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 7.3 7.4 7.5 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 8.3 8.4 8.5 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 9.3 9.4 9.5 9.6 9.7 9.8 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 172 I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53 11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 153 13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3 LEAD-FREE PACKAGE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 162 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 164 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet Please note that the list of known limitations can be found at the end of this document on page 168.
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1 INTRODUCTION
The ST72260Gx, ST72262Gx and ST72264Gx devices are members of the ST7 microcontroller family. They can be grouped as follows : - ST72264Gx devices are designed for mid-range applications with ADC, I2C and SCI interface capabilities. - ST72262Gx devices target the same range of applications but without I2C interface or SCI. - ST72260Gx devices are for applications that do not need ADC, I2C peripherals or SCI. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72F260G, ST72F262G, and ST72F264G versions feature single-voltage FLASH memory with byte-by-byte In-Circuit Programming (ICP) capabilities. Figure 1. General Block Diagram
Internal CLOCK OSC1 OSC2 MCC/RTC LVD VDD VSS RESET POWER SUPPLY CONTROL 8-BIT CORE ALU PROGRAM MEMORY (4 or 8K Bytes) ICD
ADDRESS AND DATA BUS
Under software control, all devices can be placed in WAIT, SLOW, Active-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data is located in Section 13 on page 126. Related Documentation AN1365: Guidelines for migrating ST72C254 applications to ST72F264
I2C* SCI* PORT A PA7:0 (8 bits)
MULTI OSC
SPI PORT B 16-BIT TIMER A PORT C 10-BIT ADC* 16-BIT TIMER B WATCHDOG PB7:0 (8 bits)
PC5:0 (6 bits)
RAM (256 Bytes)
*Not available on some devices, see device summary on page 1.
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2 PIN DESCRIPTION
Figure 2. 28-Pin SO Package Pinout
RESET OSC1 OSC2 SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN42/OCMP2_B/PC4 AIN32/ICAP2_B/PC3
1 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 ei0 or ei11 ei1 ei0
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD VSS ICCSEL PA0 (HS)/ICCCLK PA1 (HS)/ICCDATA PA2 (HS) PA3 (HS) PA4 (HS)/SCLI3 PA5(HS)/RDI3 PA6 (HS)/SDAI3 PA7 (HS)/TDO3 PC0/ICAP1_B/AIN02 PC1/OCMP1_B/AIN12 PC2/MCO/AIN22
(HS) 20mA high sink capability eiX associated external interrupt vector
Configurable by option byte Alternate function not available on ST72260 3 Alternate function not available on ST72260 and ST72262
Figure 3. 32-Pin SDIP Package Pinout
RESET OSC1 OSC2 SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 NC NC OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN52/EXTCLK_A/PC5 AIN42/OCMP2_B/PC4 AIN32/ICAP2_B/PC3
1 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei0 or ei11 ei1 ei0 ei1 ei0
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD VSS ICCSEL PA0 (HS)/ICCCLK PA1 (HS)/ICCDATA PA2 (HS) PA3 (HS) NC NC PA4 (HS)/SCLI3 PA5 (HS)/RDI3 PA6 (HSI/SDAI3 PA7 (HS)/TDO3 PC0/ICAP1_B/AIN02 PC1/OCMP1_B/AIN12 PC2/MCO/AIN22
(HS) 20mA high sink capability eiX associated external interrupt vector
Configurable by option byte Alternate function not available on ST72260 3 Alternate function not available on ST72260 and ST72262
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PIN DESCRIPTION (Cont'd) Figure 4. TFBGA Package Pinout (view through package) 1 2 3 4 5 6
A B C D E F
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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page 126. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: CT= CMOS 0.3 VDD/0.7 VDD with input trigger Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog - Output: OD = open drain 2), PP = push-pull Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description
Pin n Type SDIP32 SO28 BGA Pin Name Level Output Input Port / Control Input float wpu ana int Main Output Function (after reset) OD PP X
Alternate Function
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7
A3 RESET C4 OSC1 3) B3 OSC2 3) A2 PB7/SS A1 PB6/SCK B1 PB5/MISO B2 PB4/MOSI C1 NC C2 NC D1 NC
I/O CT I O I/O I/O I/O I/O CT CT CT CT X X X X
X
Top priority non maskable interrupt (active low) External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Resonator oscillator inverter output or capacitor input for RC oscillator X X X X Port B7 Port B6 Port B5 Port B4 SPI Slave Select (active low) SPI Serial Clock SPI Master In/ Slave Out Data SPI Master Out / Slave In Data
ei1 ei1 ei1 ei1
X X X X
Not Connected
10 11
8 9
C3 PB3/OCMP2_A D2 PB2/ICAP2_A
I/O I/O
CT CT CT
X X
ei1 ei1
X X
X X
Port B3 Port B2
Timer A Output Compare 2 Timer A Input Capture 2 Timer A Output Compare 1
12
10 E1 PB1 /OCMP1_A
I/O
X
ei1
X
Caution: Negative current X Port B1 injection not allowed on this pin4).
Timer A Input Capture 1
13
11 F1 PB0 /ICAP1_A
I/O
CT
X
ei1
X
Caution: Negative current X Port B0 injection not allowed on this pin4).
X Port C5 Timer A Input Clock or ADC Analog Input 5
14
12 F2 PC5/EXTCLK_A/AIN5 I/O
CT
X ei0/ei1 X
X
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Pin n Type SDIP32 SO28 BGA Pin Name
Level Output Input
Port / Control Input float wpu ana int
OD
PP
Main Output Function (after reset) X X X X X X T X T X X X X X X X Port C4 Port C3 Port C2 Port C1 Port C0 Port A7 Port A6 Port A5 Port A4
Alternate Function
15 16 17 18 19 20 21 22 23 24 25
13 E2 PC4/OCMP2_B/AIN4 14 F3 PC3/ ICAP2_B/AIN3 15 E3 PC2/MCO/AIN2 16 F4 PC1/OCMP1_B/AIN1 17 D3 PC0/ICAP1_B/AIN0 18 E4 PA7/TDO 19 F5 PA6/SDAI 20 F6 PA5 /RDI 21 E6 PA4/SCLI E5 NC D6 NC D5 NC
I/O I/O I/O I/O I/O
CT CT CT CT CT
X ei0/ei1 X X ei0/ei1 X X ei0/ei1 X X ei0/ei1 X X ei0/ei1 X X X X X ei0 ei0 ei0 ei0
Timer B Output Compare 2 or ADC Analog Input 4 Timer B Input Capture 2 or ADC Analog Input 3 Main clock output (fCPU) or ADC Analog Input 2 Timer B Output Compare 1 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 0 SCI output I2C DATA SCI input I2C CLOCK
I/O CT HS I/O CT HS I/O CT HS I/O CT HS
Not Connected
26 27
22 C6 PA3 23 D4 PA2 C5 NC
I/O CT HS I/O CT HS
X X
ei0 ei0
X X
X X
Port A3 Port A2
Not Connected B6 NC 28 29 30 31 32 24 A6 PA1/ICCDATA 25 A5 PA0/ICCCLK 26 B5 ICCSEL 27 A4 VSS 28 B4 VDD I/O CT HS I/O CT HS I S S CT X X X ei0 ei0 X X X X Port A1 Port A0 In Circuit Communication Data In Circuit Communication Clock
ICC mode pin, must be tied low Ground Main power supply
Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt input, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9 "I/O PORTS" on page 38 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSCILLATOR (MO)" on page 21 for more details. 4: For details refer to Section 13.8 on page 144
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3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 adFigure 5. Memory Map dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). The size of Flash Sector 0 and other device options are configurable by Option byte (refer to Section 15.1 on page 162). IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device. Related Documentation AN 985: Executing Code in ST7 RAM
0000h 007Fh 0080h
HW Registers (see Table 2)
0080h
RAM (256 Bytes)
017Fh 0180h
00FFh 0100h
Short Addressing RAM Zero page (128 Bytes) Stack or 16-bit Addressing RAM (128 Bytes)
8K FLASH PROGRAM MEMORY
017Fh
Reserved
DFFFh E000h
E000h
Program Memory (4K, 8 KBytes)
FFDFh FFE0h FFFFh
EFFFh F000h FFFFh
4 Kbytes SECTOR 1 4 Kbytes SECTOR 0
Interrupt & Reset Vectors (see Table 5 on page 32)
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh to 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR MCC SPI WATCHDOG ITC ISPR0 ISPR1 ISPR2 ISPR3 MISCR1 SPIDR SPICR SPICSR WDGCR SICSR MCCSR PADR PADDR PAOR Port B PBDR PBDDR PBOR Block Register Label PCDR PCDDR PCOR Register Name Port C Data Register Port C Data Direction Register Port C Option Register Reserved (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved (1 Byte) Port A Data Register Port A Data Direction Register Port A Option Register 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W R/W. Reset Status Remarks
Port C
xx000000h1) R/W 2) 00h R/W 2) R/W 2) 00h
Port A
Reserved (17 Bytes) Interrupt software priority register0 Interrupt software priority register1 Interrupt software priority register2 Interrupt software priority register3 Miscellanous register 1 SPI Data I/O Register SPI Control Register SPI Status Register Watchdog Control Register System Integrity Control / Status Register Main Clock Control / Status Register Reserved (1 Byte) I2C Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register2 I2C Data Register Reserved (2 Bytes) 00h 00h 00h 00h 00h 40h 00h R/W Read Only Read Only R/W R/W R/W R/W FFh FFh FFh FFh 00h xxh 0xh 00h 7Fh 000x 000x 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
I2C
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Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h to 006Eh 006Fh 0070h 0071h 0072h 0073h to 007Fh
Block
Register Label TACR2 TACR1 TASCSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 TBCR2 TBCR1 TBSCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR
Register Name Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Miscellanous register 2 Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register1 SCI Control Register2 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register Reserved (24 Bytes)
Reset Status 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00h x000 0000h 00h 00h 00h
Remarks R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W
TIMER A
TIMER B
SCI
ADC FLASH
ADCDRL ADCDRH ADCCSR FCSR
Data Register Low3) Data Register High3) Control/Status Register Flash Control Register Reserved (13 Bytes)
00h 00h 00h 00h
Read Only Read Only R/W R/W
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Legend: x=Undefined, R/W=Read/Write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For compatibility with the ST72C254, the ADCDRL and ADCDRH data registers are located with the LSB on the lower address (6Fh) and the MSB on the higher address (70h). As this scheme is not little Endian, the ADC data registers cannot be treated by C programs as an integer, but have to be treated as two char registers.
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features

ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection against piracy
4.3 PROGRAMMING MODES The ST7 can be programmed in three different ways: - Insertion in a programming tool. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased. - In-Circuit Programming. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. - In-Application Programming. In this mode, sector 1 can be programmed or erased without removing the device from the application
board and while the application is running. 4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. - Download ICP Driver code in RAM from the ICCDATA pin - Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC interface ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These pins are: - RESET: device reset - VSS: device power supply ground - ICCCLK: ICC output serial clock pin - ICCDATA: ICC input serial data pin - ICCSEL: ICC selection (not required on devices without ICCSEL pin) - OSC1: main clock input for external source (not required on devices without OSC1/OSC2 pins) - VDD: application board power supply (optional, see Note 3) Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Figure 6. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) APPLICATION BOARD
Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
(See Note 3)
9 10
7 8
5 6
3 4
1 2
APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O VSS ICCSEL RESET ICCDATA ICCCLK
VDD
OSC2
OSC1 ST7
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FLASH PROGRAM MEMORY (Cont'd) 4.5 Memory Protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In flash devices, this protection is removed by reprogramming the option. In this case the program memory is automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: - In Flash devices it is enabled and removed through the FMP_R bit in the option byte. - In ROM devices it is enabled by mask option specified in the Option List. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. AN1477: Emulated data EEPROM with XFlash memory AN1576: IAP drivers for ST7 HDFlash or XFlash MCUs AN1575: On Board Programming methods for ST7 HDFlash or XFlash MCUs AN1070: Checksum self checking capability 4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)
7 0 0 0 0 0 OPT LAT 0 PGM
Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES

5.3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 7. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 128 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 8. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8 - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 017Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 017Fh Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10. For more details, refer to dedicated parametric section. Main Features Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) Reset Sequence Manager (RSM) Multi-Oscillator Clock Management (MO) - 4 Crystal/Ceramic resonator oscillators - 1 Internal RC oscillator System Integrity Management (SI) - Main supply Low Voltage Detector (LVD) - Auxiliary Voltage Detector (AVD) with interrupt capability for monitoring the main supply
6.1 PHASE LOCKED LOOP If the clock frequency input to the PLL is in the 2 to 4 MHz range, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required. See "PLL Characteristics" on page 139. Figure 9. PLL Block Diagram
PLL x 2
fOSC
0 fOSC2 1
/2
PLL OPTION BIT
Figure 10. Clock, Reset and Supply Block Diagram
MISCR1 Register SLOW MODE SELECTION MULTIOSCILLATOR OSC1 (MO) SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) WATCHDOG AVD Interrupt Request SICSR 0 AVD AVD LVD F RF IE WDG RF TIMER (WDG) 0 MAIN CLOCK CONTROLLER WITH REALTIME CLOCK (MCC/RTC)
fCPU to CPU and Peripherals
OSC2
fOSC
PLL (option)
fOSC2
0
0
LOW VOLTAGE VSS VDD DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
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6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multioscillator block: an external source 5 crystal or ceramic resonator oscillators an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 3. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effects Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 15.1 on page 162 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Related documentation AN1530: Accurate timebase for low cost ST7 applications with internal RC. Table 3. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OSC1 OSC2
EXTERNAL SOURCE
Crystal/Ceramic Resonators
ST7 OSC1 OSC2
CL1
LOAD CAPACITORS
CL2
Internal RC Oscillator
ST7 OSC1 OSC2
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6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 12: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: Active Phase depending on the RESET source 4096 CPU clock cycle delay (selected by option byte) RESET vector fetch The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. Figure 12. Reset Block Diagram The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
VDD
RON
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET LVD RESET
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RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.3.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Low Voltage Detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDDFigure 13. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
LVD RESET
EXTERNAL RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (4096 TCPU) VECTOR FETCH
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6.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains group the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1 on page 123 for further details. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling The LVD function is illustrated in Figure 14. The voltage threshold can be configured by option byte to be low, medium or high. Figure 14. Low Voltage Detector vs Reset
VDD
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: - under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected by option byte. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 91 on page 151 and note 6. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.
Vhys VIT+ VIT-
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT- and VIT+ reference value and the VDD main supply. The VITreference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (VDF) in the SICSR register. This bit is read only. Caution: The AVD functions only if the LVD is enabled through the option byte. 6.4.2.1 Monitoring the VDD Main Supply The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 15.1 on page 162). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). Figure 15. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vhyst
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 15. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then: - If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached. - If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
trv VOLTAGE RISE TIME
AVDF bit AVD INTERRUPT REQUEST IF AVDIE bit = 1
0
1
RESET VALUE
1
0
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.3 Low Power Modes
Mode WAIT HALT Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. Interrupt Event AVD event Enable Event Control Flag Bit AVDF AVDIE Exit from Wait Yes Exit from Halt No
set and the interrupt mask in the CC register is reset (RIM instruction).
6.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF Reset Value: 000x 000x (00h) bit value is undefined.
7 0 AVD IE AVD F LVD RF 0 0 0 0 WDG RF
Bit 3:1 = Reserved, must be kept cleared. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LVDRF 0 0 1 WDGRF 0 1 X
Bit 7 = Reserved, always read as 0. Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. 0: VDD over VIT+(AVD) threshold 1: VDD under VIT-(AVD) threshold Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See
Address (Hex.) 0025h Register Label SICSR Reset Value 7 6 AVDIE 0 5 AVDF 0
Application Notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
4 LVDRF x
3
2
1
0 WDGRF x
0
0
0
0
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7 INTERRUPTS
7.1 INTRODUCTION The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: - Up to 4 software programmable nesting levels - Up to 16 interrupt vectors fixed by hardware - 2 non-maskable events: RESET and TRAP This interrupt management is based on: - Bit 5 and bit 3 of the CPU CC register (I1:0), - Interrupt software priority registers (ISPRx), - Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 4). The processing flow is shown in Figure 16 Figure 16. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y
When an interrupt request has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 4. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
Interrupt has the same or a lower software priority than current one
I1:0 Interrupt has a higher software priority than current one
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: - the highest software priority interrupt is serviced, - if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 17 describes this decision process. Figure 17. Priority Decision Process
PENDING INTERRUPTS
3). These sources allow the processor to exit HALT mode. TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart on Figure 16 as a TLI. RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details. Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the Miscellaneous registers (MISCRx). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt vector request an interrupt simultaneously, the interrupt vector will be serviced. Software can read the pin levels to identify which pin(s) are the source of the interrupt. If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET and TRAP are non-maskable and they can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET and TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 16). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level
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INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 17. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. 7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 18 and Figure 19 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 19. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure. Note: TLI (Top Level Interrupt) is not available in this product. Related Documentation AN1044: Multiple interrupt source management for ST7 MCUs
Figure 18. Concurrent Interrupt Management
SOFTWARE PRIORITY LEVEL IT2 IT1 IT4 IT3 TLI IT0 I1 I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 19. Nested Interrupt Management
SOFTWARE PRIORITY LEVEL
TLI
IT2
IT1
IT4
IT3
IT0
I1
I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 20 BYTES
USED STACK = 10 BYTES
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INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR0 ISPR1 ISPR2 ISPR3
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bits 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 I1_3 I1_7 I0_3 I0_7 I1_2 I1_6 I0_2 I0_6 I1_1 I1_5 I0_1 I0_5 I0_9 I1_0 I1_4 I1_8 0 I0_0 I0_4 I0_8
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TRAP and RESET events are non maskable sources and can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. - Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector Address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx Bits ei0 ei1 ... Not used
- Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. - Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd) Table 5. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SCI I2C SPI TIMER A MCC TIMER B AVD ei0 ei1 Reset Software Interrupt External Interrupt Port A7..0 (C5..01) External Interrupt Port B7..0 (C5..01) Not used SPI Peripheral Interrupts TIMER A Peripheral Interrupts Time base interrupt TIMER B Peripheral Interrupts Auxiliary Voltage Detector interrupt Not used Not used SCI Peripheral Interrupt I2C Peripheral Interrupt Not Used Not Used SCISR I2CSRx Lowest Priority no no SPISR TASR MCCSR TBSR SICSR yes no yes no N/A Description Register Label Priority Order Highest Priority Exit from HALT yes no yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Note 1. Configurable by option byte. Table 6. Nested Interrupts Register Map and Reset Values
Address (Hex.) Register Label 7 SPI 001Ch ISPR0 Reset Value I1_3 1 AVD 001Dh ISPR1 Reset Value I1_7 1 I2C 001Eh ISPR2 Reset Value I1_11 1 I0_11 1 I1_10 1 I0_7 1 I0_3 1 6 5 Not Used I1_2 1 I0_2 1 I1_1 1 MCC I1_5 1 I0_5 1 4 3 EI1 I0_1 1 I1_0 1 2 1 EI0 I0_0 1 0
TIMERB I1_6 1 SCI I0_10 1 I0_6 1
TIMERA I1_4 1 I0_4 1
Not Used I1_9 1 I0_9 1
Not Used I1_8 1 I0_8 1
Not Used 001Fh ISPR3 Reset Value 1 1 1 1 I1_13 1 I0_13 1
Not Used I1_12 1 I0_12 1
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 20). After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 20. Power Saving Mode Transitions
High RUN
fCPU
8.2 SLOW MODE This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MISR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when enterring the WAIT mode while the device is already in SLOW mode. Figure 21. SLOW Mode Clock Transitions
fOSC2/2 fOSC2/4 fOSC2
SLOW
fOSC2 MISCR1
WAIT SLOW WAIT HALT Low POWER CONSUMPTION
CP1:0 SMS
00
01
NEW SLOW FREQUENCY REQUEST
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I [1:0] bits in the CC register are forced to `10b', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 22. Figure 22. WAIT Mode Flowchart
OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON OFF 0
WFI INSTRUCTION
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 1 Y
4096 CPU CLOCK CYCLE DELAY
OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 1)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC register are set during the interrupt routine and cleared when the CC register is popped.
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8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR OIE bit 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode
Figure 23. ACTIVE-HALT Timing Overview
RUN ACTIVE HALT 4096 CPU CYCLE DELAY 1) RESET OR INTERRUPT RUN
HALT INSTRUCTION [MCCSR.OIE=1]
FETCH VECTOR
Figure 24. ACTIVE-HALT Mode Flowchart
HALT INSTRUCTION (MCCSR.OIE=1) OSCILLATOR ON PERIPHERALS 2) OFF CPU OFF 10 I[1:0] BITS N RESET N INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS OFF CPU ON I[1:0] BITS XX 4) 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 4) FETCH RESET VECTOR OR SERVICE INTERRUPT Y
8.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set. The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 5, "Interrupt Mapping," on page 32) or a RESET. When exiting ACTIVE-HALT mode by means of an interrupt, no 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 5, "Interrupt Mapping," on page 32 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.5 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 26). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 5, "Interrupt Mapping," on page 32) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25). When entering HALT mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 15.1 "OPTION BYTES" on page 162 for more details). Figure 25. HALT Mode Timing Overview
RUN HALT 4096 CPU CYCLE DELAY RUN FETCH RESET VECTOR OR SERVICE INTERRUPT
Figure 26. HALT Mode Flowchart
HALT INSTRUCTION ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I[1:0] BITS 0 0 WATCHDOG DISABLE
N RESET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 1
4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 4)
HALT INSTRUCTION
RESET OR INTERRUPT
FETCH VECTOR
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 5, "Interrupt Mapping," on page 32 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC register are set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.5.0.1 Halt Mode Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). Related Documentation AN 980: ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke AN1014: How to Minimize the ST7 Power Consumption AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode
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9 I/O PORTS
9.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for onchip peripherals or analog input. 9.2 FUNCTIONAL DESCRIPTION A Data Register (DR) and a Data Direction Register (DDR) are always associated with each port. The Option Register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer to the Port Configuration table for device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port. Figure 27 shows the generic I/O block diagram. 9.2.1 Input Modes Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: floating or pull-up. Refer to I/O Port Implementation section for configuration. Notes: 1. Writing to the DR modifies the latch value but does not change the state of the input pin. 2. Do not use read/modify/write instructions (BSET/BRES) to modify the DR register. External Interrupt Function Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O generates an interrupt request via the corresponding interrupt vector (eix). Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control Register (EICR) or the Miscellaneous Register controls this sensitivity, depending on the device. A device may have up to 7 external interrupts. Several pins may be tied to one external interrupt vector. Refer to Pin Description to see which ports have external interrupts. If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Modifying the sensitivity bits will clear any pending interrupts. 9.2.2 Output Modes Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: push-pull or opendrain. Refer to I/O Port Implementation section for configuration. DR Value and Output Pin Status
DR 0 1 Push-Pull VOL VOH Open-Drain VOL Floating
9.2.3 Alternate Functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral's control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O's state is readable by addressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.
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I/O PORTS (Cont'd) Figure 27. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT
From on-chip peripheral
1 0
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
ALTERNATE ENABLE BIT DR
DDR
PULL-UP CONDITION
DATA BUS
PAD
OR OR SEL
If implemented
N-BUFFER DDR SEL CMOS SCHMITT TRIGGER
DIODES (see table below) ANALOG INPUT
DR SEL
1 0
ALTERNATE INPUT
Combinational Logic To on-chip peripheral
EXTERNAL INTERRUPT REQUEST (eix)
SENSITIVITY SELECTION
FROM OTHER BITS Note: Refer to the Port Configuration
table for device specific information.
Table 7. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
Output
NI (see note)
Legend:NI - not implemented Off - implemented not activated On - implemented and activated
Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VOL is implemented to protect the device against positive stress.
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I/O PORTS (Cont'd) Table 8. I/O Configurations
Hardware Configuration
VDD RPU PAD NOTE 3 PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
FROM OTHER PINS INTERRUPT COMBINATIONAL POLARITY LOGIC SELECTION CONDITION
ALTERNATE INPUT To on-chip peripheral EXTERNAL INTERRUPT SOURCE (eix)
ANALOG INPUT
OPEN-DRAIN OUTPUT 2)
VDD RPU PAD
NOTE 3 DR REGISTER ACCESS
DR REGISTER
R/W
DATA BUS
PUSH-PULL OUTPUT 2)
VDD RPU PAD
NOTE 3
DR REGISTER ACCESS
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE BIT
ALTERNATE OUTPUT From on-chip peripheral
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. 3. For true open drain, these elements are not implemented.
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I/O PORTS (Cont'd) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input. Analog Recommendations Do not change the voltage level or loading on any I/O while conversion is in progress. Do not have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 28. Other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. Figure 28. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
9.4 UNUSED I/O PINS Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8. 9.5 LOW POWER MODES
Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
9.6 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx ORx Exit from Wait Yes Exit from Halt Yes
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
Related Documentation AN 970: SPI Communication between ST7 and EEPROM AN1045: S/W implementation of I2C bus master AN1048: Software LCD driver
XX
= DDR, OR
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I/O PORTS (Cont'd) 9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION The I/O port register configurations are summarised as follows. Interrupt Ports PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
True Open Drain Interrupt Ports PA6, PA4 (without pull-up)
MODE floating input floating interrupt input open drain (high sink ports) DDR 0 0 1 OR 0 1 X
Table 9. Port Configuration
Input (DDR = 0) Port Pin Name OR = 0 PA7 PA6 PA5 PA4 PA3:0 PB7:0 PC5:0 floating floating floating floating floating floating floating OR = 1 pull-up interrupt floating interrupt pull-up interrupt floating interrupt pull-up interrupt pull-up interrupt pull-up interrupt OR = 0 OR = 1 High-Sink open drain push-pull true open-drain open drain push-pull true open-drain open drain push-pull open drain push-pull open drain push-pull Output (DDR = 1)
Port A
Yes
Port B Port C
No
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I/O PORTS (Cont'd) 9.8 I/O PORT REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register PxDR with x = A, B or C. Read/Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B or C. Read/Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bits 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows always having the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B or C. Read/Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bits 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Pull-up input with or without interrupt Output mode: 0: Output open drain (with P-Buffer unactivated) 1: Output push-pull (when available)
Bits 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 10. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0
Reset Value of all I/O port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah PCDR PCDDR PCOR PBDR PBDDR PBOR PADR PADDR PAOR
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
MSB
LSB
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10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions. 10.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register and the OPTION BYTE. This control allows you to have two fully independent external interrupt source sensitivities with configurable sources (using the EXTIT option bit) as shown in Figure 29 and Figure 30. Each external interrupt source can be generated on four different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level To guarantee correct functionality, the sensitivity bits in the MISCR1 register must be modified only when the I[1:0] bits in the CC register are set to 1 (interrupt masked). See Section 9.8 "I/O PORT REGISTER DESCRIPTION" on page 43 and Section 10.3 "MISCELLANEOUS REGISTER DESCRIPTION" on page 46 for more details on the programming.
PA0 PC5
Figure 29. Ext. Interrupt Sensitivity (EXTIT=0)
MISCR1 ei0 INTERRUPT SOURCE IS00 IS01
PA7
SENSITIVITY CONTROL
PC0 MISCR1 ei1 INTERRUPT SOURCE IS10 IS11
PB7
SENSITIVITY CONTROL
PB0
Figure 30. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1 ei0 INTERRUPT SOURCE IS00 IS01
PA7
SENSITIVITY CONTROL
PA0
10.2 I/O PORT ALTERNATE FUNCTIONS The MISCR registers manage four I/O port miscellaneous alternate functions: Main clock signal (fCPU) output on PC2 SPI pin configuration: - SS pin internal control to use the PB7 I/O port function while the SPI is active. - Master output capability on the MOSI pin (PB4) deactivated while the SPI is active. - Slave output capability on the MISO pin (PB5) deactivated while the SPI is active. These functions are described in detail in the Section 10.3 "MISCELLANEOUS REGISTER DESCRIPTION" on page 46.
PB7 ei1 INTERRUPT SOURCE
MISCR1 IS10 IS11
PB0 PC5
SENSITIVITY CONTROL
PC0
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MISCELLANEOUS REGISTERS (Cont'd) 10.3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 MCO IS01 IS00 CP1 CP0 0 fCPU in SLOW mode SMS fOSC2 / 2 fOSC2 / 4 fOSC2 / 8 CP1 0 1 0 1 CP0 0 0 1 1
Bits 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the various slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software
Bits 7:6 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei1 external interrupts. These two bits can be written only when the I[1:0] bits in the CC register are set to 1 (interrupt masked). ei1: Port B (C optional)
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge IS11 IS10 0 0 1 1 0 1 0 1
fOSC2 / 16
Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details.
Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the PC2 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) Bits 4:3 = IS0[1:0] ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts. These two bits can be written only when the I[1:0] bits inthe CC register are set to 1 (interrupt masked). ei0: Port A (C optional)
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge IS01 IS00 0 0 1 1 0 1 0 1
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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 MOD SOD SSM 0 SSI
Caution: This register has been provided for compatibility with the ST72254 family only. The same bits are available in the SPICSR register. New applications must use the SPICSR register. Do not use both registers, this will cause the SPI to malfunction. Bits 7:4 = Reserved always read as 0 Bits 3 = MOD SPI Master Output Disable This bit is set and cleared by software. When set, it disables the SPI Master (MOSI) output signal. 0: SPI Master Output enabled. 1: SPI Master Output disabled. Bit 2 = SOD SPI Slave Output Disable This bit is set and cleared by software. When set it disable the SPI Slave (MISO) output signal. 0: SPI Slave Output enabled. 1: SPI Slave Output disabled. Bit 1 = SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is input from the external SS pin. 1: I/O mode, the level of the SPI SS signal is read from the SSI bit. Bit 0 = SSI SS internal mode This bit replaces the SS pin of the SPI when the SSM bit is set to 1. (see SPI description). It is set and cleared by software.
Table 11. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value 7 IS11 0 0 6 IS10 0 0 5 MCO 0 0 4 IS01 0 0 3 IS00 0 MOD 0 2 CP1 0 SOD 0 1 CP0 0 SSM 0 0 SMS 0 SSI 0
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11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 11.1.2 Main Features Programmable free-running downcounter Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte 11.1.3 Functional Description The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h: - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 32. Approximate Timeout Duration). The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 33). Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset.
Figure 31. Watchdog Block Diagram
RESET
fOSC2 MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR) DIV 64 WDGA T6 T5 T4 T3 T2 T1 T0
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC RTC COUNTER MSB
11 65
LSB
0
TB[1:0] bits (MCCSR Register)
WDG PRESCALER DIV 4
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WATCHDOG TIMER (Cont'd) 11.1.4 How to Program the Watchdog Timeout Figure 32 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If Figure 32. Approximate Timeout Duration 3F 38 30
more precision is needed, use the formulae in Figure 33. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.
CNT Value (hex.)
28 20 18
10 08 00 1.5 18 34 50 65 82 98 114 128 Watchdog timeout (ms) @ 8 MHz. fOSC2
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WATCHDOG TIMER (Cont'd) Figure 33. Exact Timeout Duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2=8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register
TB1 Bit TB0 Bit (MCCSR Reg.) (MCCSR Reg.) 0 0 0 1 1 0 1 1 Selected MCCSR Timebase 2ms 4ms 10ms 25ms MSB 4 8 20 49 LSB 59 53 35 54
To calculate the minimum Watchdog Timeout (tmin): IF CNT < MSB ------------4
THEN t min = t min0 + 16384 x CNT x tosc2 ELSE t min = t min0 + 16384 x CNT - 4CNT + ( 192 + LSB ) x 64 x 4CNT ------------------------------ MSB MSB
x t osc2
To calculate the maximum Watchdog Timeout (tmax): IF CNT MSB ------------4
THEN t max = t max0 + 16384 x CNT x t osc2 ELSE t max = t max0 + 16384 x CNT - 4CNT + ( 192 + LSB ) x 64 x 4CNT ------------------------------ MSB MSB
x t osc2
Note: In the above formulae, division results must be rounded down to the next integer value. Example: With 2ms timeout selected in MCCSR register
Value of T[5:0] Bits in WDGCR Register (Hex.) 00 3F Min. Watchdog Timeout (ms) tmin 1.496 128 Max. Watchdog Timeout (ms) tmax 2.048 128.552
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WATCHDOG TIMER (Cont'd) 11.1.5 Low Power Modes Mode SLOW WAIT Description No effect on Watchdog. No effect on Watchdog.
OIE bit in MCCSR register WDGHALT bit in Option Byte No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 11.1.7 below. A reset is generated. No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.
0
0
HALT
0
1
1
x
11.1.6 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description. 11.1.7 Using Halt Mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. 11.1.8 Interrupts None.
11.1.9 Register Description CONTROL REGISTER (WDGCR) Read/Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB). These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
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Table 12. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0024h Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) The Main Clock Controller consists of a real time clock timer with interrupt capability 11.2.1 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC2 are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 8.4 "ACTIVE-HALT AND HALT MODES" on page 35 for more details.
Figure 34. Main Clock Controller (MCC/RTC) Block Diagram
fOSC2 RTC COUNTER TO WATCHDOG
TB1 TB0 OIE MCCSR
OIF MCC/RTC INTERRUPT
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) 11.2.2 Low Power Modes Bit 3:2 = TB[1:0] Time base control
Mode WAIT Description No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability.
These bits select the programmable divider time base. They are set and cleared by software.
Time Base Counter Prescaler f OSC2 =4MHz fOSC2=8MHz 16000 32000 80000 200000 4ms 8ms 20ms 50ms 2ms 4ms 10ms 25ms TB1 0 0 1 1 TB0 0 1 0 1
ACTIVEHALT
HALT
11.2.3 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Yes Exit from Halt No 1)
A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode. Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.
Note: The MCC/RTC interrupt wakes up the MCU from ACTIVE-HALT mode, not from HALT mode. 11.2.4 Register Description MCC CONTROL/STATUS REGISTER (MCCSR) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 TB1 TB0 OIE 0 OIF
Bit 7:4 = reserved Table 13. Main Clock Controller Register Map and Reset Values
Address (Hex.) 0025h 0026h Register Label SICSR Reset Value MCCSR Reset Value 7 6 AVDIE 0 0 5 AVDF 0 0 4 LVDRF x 0 3 2 1 0 WDGRF x OIF 0
0 0
0 TB1 0
0 TB0 0
0 OIE 0
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11.3 16-BIT TIMER 11.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some devices of the ST7 family have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a Device reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In the devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 11.3.2 Main Features Programmable prescaler: fCPU divided by 2, 4 or 8. Overflow status flag and maskable interrupt External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge Output compare functions with - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt Input capture functions with - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt Pulse width modulation mode (PWM) One pulse mode Reduced Power Mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 35. *Note: Some timer pins may not available (not bonded) in some devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 11.3.3 Functional Description 11.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 14 Clock Control Bits. The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 35. Timer Block Diagram
INTERNAL BUS fCPU 16-BIT TIMER PERIPHERAL INTERFACE 8 low 8-bit buffer EXEDG 16 1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 16 INPUT CAPTURE REGISTER 2 16 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8
8 high
OUTPUT COMPARE CIRCUIT 6
EDGE DETECT CIRCUIT1
ICAP1 pin
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 TIMD
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Control/Status Register) CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See Device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte Other instructions Read At t0 +t LS Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (Device awakened by an interrupt) or from the reset count (Device awakened by a Reset). 11.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 36. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 37. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 38. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000
Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is running.
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16-BIT TIMER (Cont'd) 11.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition detected by the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 14 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input).
When an input capture occurs: - ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 40). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One pulse Mode and PWM mode only the input capture 2 can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 39. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 40. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The active edge is the rising edge. FF03 FF01 FF02 FF03
Note: The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3 CPU clock cycles. This depends on the moment when the ICAP event happens relative to the timer clock.
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16-BIT TIMER (Cont'd) 11.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCIE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
fCPU
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 14 Clock Control Bits) If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 14 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 42 on page 63). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 43 on page 63). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 41. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in both one pulse mode and PWM mode.
16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit
OC1E OC2E
CC1
CC0
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 42. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 43. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 11.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 14 Clock Control Bits). One pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 14 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) = External timer clock frequency (in hertz) fEXT When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 44). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
OCMP1 = OLVL1
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1 register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin and the ICF1 bit is set. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 44. One Pulse Mode Timing Example
IC1R COUNTER ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 01F8 FFFC FFFD FFFE 01F8 2ED0 2ED1 2ED2 2ED3 2ED3 FFFC FFFD
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 45. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2
2ED0 2ED1 2ED2
34E2
FFFC
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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16-BIT TIMER (Cont'd) 11.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are loaded in their respective shadow registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). The shadow registers contain the reference values for comparison in PWM "double buffering" mode. Note: There is a locking mechanism for transferring the OCiR value to the buffer. After a write to the OCiHR register, transfer of the new compare value to the buffer is inhibited until OCiLR is also written. Unlike in Output Compare mode, the compare function is always enabled in PWM mode. Procedure To use pulse width modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits). Pulse Width Modulation cycle When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 14 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) = External timer clock frequency (in hertz) fEXT The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 45) Notes: 1. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 2. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.
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16-BIT TIMER (Cont'd) 3. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and 11.3.4 Low Power Modes
Mode WAIT
ICF1 can also generates interrupt if ICIE is set. 4. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.
Description No effect on 16-bit Timer. Timer interrupts cause the Device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the Device is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the Device is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the Device is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
11.3.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 11.3.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode PWM Mode
1) 2)
Input Capture 1 Yes Yes No No
AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes No Partially 2) Not Recommended1) 3) Not Recommended No No
See note 4 in Section 11.3.3.5 "One Pulse Mode" on page 64 See note 5 in Section 11.3.3.5 "One Pulse Mode" on page 64 3) See note 4 in Section 11.3.3.6 "Pulse Width Modulation Mode" on page 66
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16-BIT TIMER (Cont'd) 11.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 14. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) CONTROL/STATUS REGISTER (CSR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 0
Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled Bits 1:0 = Reserved, must be kept cleared.
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.
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16-BIT TIMER (Cont'd) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 15. 16-Bit Timer Register Map and Reset Values
Address (Hex.) Register Label 7 ICIE 0 OC1E 0 ICF1 x MSB MSB MSB MSB MSB MSB MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 x 5 TOIE 0 OPM 0 TOF x 4 FOLV2 0 PWM 0 ICF2 x 3 FOLV1 0 CC1 0 OCF2 x 2 OLVL2 0 CC0 0 TIMD 0 1 IEDG1 0 IEDG2 0 x 0 OLVL1 0 EXEDG 0 x LSB LSB LSB LSB LSB LSB LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB -
Timer A: 32 CR1 Timer B: 42 Reset Value Timer A: 31 CR2 Timer B: 41 Reset Value Timer A: 33 CSR Timer B: 43 Reset Value Timer A: 34 IC1HR Timer B: 44 Reset Value Timer A: 35 IC1LR Timer B: 45 Reset Value Timer A: 36 OC1HR Timer B: 46 Reset Value Timer A: 37 OC1LR Timer B: 47 Reset Value Timer A: 3E OC2HR Timer B: 4E Reset Value Timer A: 3F OC2LR Timer B: 4F Reset Value Timer A: 38 CHR Timer B: 48 Reset Value Timer A: 39 CLR Timer B: 49 Reset Value Timer A: 3A ACHR Timer B: 4A Reset Value Timer A: 3B ACLR Timer B: 4B Reset Value Timer A: 3C ICHR2 Timer B: 4C Reset Value Timer A: 3D ICLR2 Timer B: 4D Reset Value
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1 -
1 -
1 -
1 -
1 -
0 -
-
-
-
-
-
-
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16-BIT TIMER (Cont'd) Related Documentation AN 973: SCI software communications using 16bit timer AN 974: Real Time Clock with ST7 Timer Output Compare AN 976: Driving a buzzer through the ST7 Timer PWM function AN1041: Using ST7 PWM signal to generate analog input (sinusoid) AN1046: UART emulation software AN1078: PWM duty cycle switch implementing true 0 or 100 per cent duty cycle AN1504: Starting a PWM signal directly at high level using the ST7 16-Bit timer
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11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 Main Features Full duplex synchronous transfers (on 3 lines) Simplex synchronous transfers (on 2 lines) Master or slave operation Six master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) SS Management by software or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 General Description Figure 46 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: - SPI Control Register (SPICR) - SPI Control/Status Register (SPICSR) - SPI Data Register (SPIDR) The SPI is connected to external devices through 4 pins: - MISO: Master In / Slave Out data - MOSI: Master Out / Slave In data - SCK: Serial Clock out by SPI masters and input by SPI slaves - SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master Device.
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 46. Serial Peripheral Interface Block Diagram
Data/Address Bus SPIDR Read Read Buffer Interrupt request
MOSI MISO
8-Bit Shift Register
7 SPIF WCOL OVR MODF 0
SPICSR
SOD SSM
0 SSI
SOD bit
Write
SS
SPI STATE CONTROL
7 SPIE
1 0
SCK
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 47. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device reFigure 47. Single Master/ Single Slave Application
sponds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 50) but master and slave must be programmed with the same timing mode.
MASTER MSBit LSBit MISO MISO MSBit
SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK SS +5V
SCK SS
Not used if SS is managed by software
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 49) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: - SS internal must be held high continuously
In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 48): If CPHA=1 (data latched on 2nd clock edge): - SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the in the SPICSR register) If CPHA=0 (data latched on 1st clock edge): - SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.4.5.3).
Figure 48. Generic SS Timing Diagram
MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1)
Byte 1
Byte 2
Byte 3
Figure 49. Hardware/Software Slave Select Management SSM bit
SSI bit SS external pin
1 0
SS internal
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit ) may be not taken into account): 1. Write to the SPICR register: - Select the clock frequency by configuring the SPR[2:0] bits. - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 50 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: - Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: - Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). The transmit sequence begins when software writes a byte in the SPIDR register. 11.4.3.4 Master Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 11.4.3.5 Slave Mode Operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 50). Note: The slave must have the same CPOL and CPHA settings as the master. - Manage the SS pin as described in Section 11.4.3.2 and Figure 48. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. 11.4.3.6 Slave Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.4.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 50). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 50. Data Clock Timing Diagram
Figure 50, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
CPHA =1
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.5 Error Flags 11.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: - The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the Device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the Device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device, the MODF bit can not be set, but in a multi master configuration the Device can be in slave mode with the MODF bit set. The MODF bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application default state.
11.4.5.2 Overrun Condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs: - The OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. 11.4.5.3 Write Collision Error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Section 11.4.3.2 "Slave Select Management" on page 78. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the CPU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 51).
Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR
RESULT
2nd Step
Read SPIDR
SPIF =0 WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Read SPICSR
RESULT
Read SPIDR
WCOL=0
Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.5.4 Single Master and Multimaster Configurations There are two types of SPI systems: - Single Master System - Multimaster System Single Master System A typical single master system may be configured, using a device as the master and four devices as slaves (see Figure 52). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.
For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Multi-Master System A multi-master system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system. The multi-master system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register.
Figure 52. Single Master / Multiple Slave Configuration
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
MOSI MISO SCK Master Device 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.6 Low Power Modes
Mode WAIT Description No effect on SPI. SPI interrupt events cause the Device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the Device is woken up by an interrupt with "exit from HALT mode" capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device.
SS pin or the SSI bit in the SPICSR register) is low when the Device enters Halt mode. So if Slave selection is configured as external (see Section 11.4.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode. 11.4.7 Interrupts
Interrupt Event Event Flag Enable Control Bit Exit from Wait Yes SPIE Yes Yes Exit from Halt Yes No No
HALT
SPI End of TransSPIF fer Event Master Mode MODF Fault Event Overrun Error OVR
11.4.6.1 Using the SPI to wake-up the Device from Halt mode In slave configuration, the SPI is able to wake-up the Device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake-up the Device from Halt mode only if the Slave Select signal (external
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh)
7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 0 SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register) Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.4.5.1 "Master Mode Fault (MODF)" on page 81). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 16 SPI Master mode SCK Frequency. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. Bit 4 = MSTR Master Mode. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.4.5.1 "Master Mode Fault (MODF)" on page 81). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 16. SPI Master mode SCK Frequency Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
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SERIAL PERIPHERAL INTERFACE (Cont'd) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)
7 SPIF WCOL OVR MODF SOD SSM 0 SSI
Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 11.4.3.2 "Slave Select Management" on page 78. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the Device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 51). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.4.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.4.5.1 "Master Mode Fault (MODF)" on page 81). An SPI interrupt can be generated if SPIE=1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared.
The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 46).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 17. SPI Register Map and Reset Values
Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPICSR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x SSI 0
x SPE 0 WCOL 0
x SPR2 0 OR 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x SOD 0
x SPR1 x SSM 0
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11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 11.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 11.5.2 Main Features Full duplex, asynchronous communications NRZ standard format (Mark/Space) Dual baud rate generator systems Independently programmable transmit and receive baud rates up to 500K baud. Programmable data word length (8 or 9 bits) Receive buffer full, Transmit buffer empty and End of Transmission flags Two receiver wake-up modes: - Address bit (MSB) - Idle line Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver Four error detection flags: - Overrun error - Noise error - Frame error - Parity error Five interrupt sources with flags: - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error detected Parity control: - Transmits parity bit - Checks parity of received data byte Reduced power consumption mode 11.5.3 General Description The interface is externally connected to another device by two pins (see Figure 54): - TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. - RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as frames comprising: - An Idle Line prior to transmission or reception - A start bit - A data word (8 or 9 bits) least significant bit first - A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: - A conventional type for commonly-used baud rates, - An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 53. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Transmit Data Register (TDR) TDO Transmit Shift Register RDI
Received Data Register (RDR)
Received Shift Register
CR1
R8 T8 SCID M WAKE PCE PS PIE
TRANSMIT CONTROL
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
CR2
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE
SR
SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE
fCPU
CONTROL
/16
/PR BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 11.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 53. It contains 6 dedicated registers: - Two control registers (SCICR1 & SCICR2) - A status register (SCISR) - A baud rate register (SCIBRR) - An extended prescaler receiver register (SCIERPR) - An extended prescaler transmitter register (SCIETPR) Refer to the register descriptions in Section 11.5.7for the definitions of each bit.
11.5.4.1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 53). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of "1"s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving "0"s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra "1" bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator.
Figure 54. Word Length Programming 9-bit Word length (M bit is set) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8
Next Data Frame
Next Stop Start Bit Bit Start Bit
Idle Frame
Break Frame
Extra '1'
Start Bit
8-bit Word length (M bit is reset) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible Parity Bit Bit7 Stop Bit
Next Data Frame
Next Start Bit Start Bit Extra Start Bit '1'
Idle Frame Break Frame
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 11.5.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 53). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the SCIBRR and the SCIETPR registers. - Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. - Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: - The TDR register is empty. - The data transfer is beginning. - The next data can be written in the SCIDR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 54). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 11.5.4.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 53). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the SCIBRR and the SCIERPR registers. - Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: - The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. - The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SPI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the
RDR register as long as the RDRF bit is not cleared. When a overrun error occurs: - The OR bit is set. - The RDR content will not be lost. - The shift register will be overwritten. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise Error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame: - The NF flag is set at the rising edge of the RDRF bit. - Data is transferred from the Shift register to the SCIDR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. See also Section 11.5.4.10.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 55. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER CLOCK EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER RECEIVER CLOCK EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER
fCPU
TRANSMITTER RATE CONTROL
/16
/PR SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Framing Error A framing error is detected when: - The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. - A break is received. When the framing error is detected: - the FE bit is set by hardware - Data is transferred from the Shift register to the SCIDR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. 11.5.4.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU (16*PR)*TR Rx = fCPU (16*PR)*RR
Note: the extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows: fCPU fCPU Rx = Tx = 16*ERPR*(PR*RR) 16*ETPR*(PR*TR) with: ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,.. 255 (see SCIERPR register) 11.5.4.6 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by one of the following two ways: - by Idle Line detection if the WAKE bit is reset, - by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a "1" as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode.
with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If fCPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud. Note: the baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. 11.5.4.5 Extended Baud Rate Generation The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility. The extended baud rate generator block diagram is described in the Figure 55. The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 11.5.4.7 Parity Control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 18. Table 18. Frame Formats
M bit 0 0 1 1 PCE bit 0 1 0 1 SCI frame | SB | 8 bit data | STB | | SB | 7-bit data | PB | STB | | SB | 9-bit data | STB | | SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit Even parity: the parity bit is calculated to obtain an even number of "1s" inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity: the parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the interface checks if the received data byte has an
even number of "1s" if even parity is selected (PS=0) or an odd number of "1s" if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. 11.5.4.8 SCI Clock Tolerance During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be "1", but the Noise Flag bit is be set because the three samples values are not the same. Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples will be at 28s, 32s & 36s respectively (the first sample starting ideally at 0s). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4us. This means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchronization with the internal sampling clock).
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 11.5.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: - DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). - DQUANT: Error due to the baud rate quantisation of the receiver. - DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. - DTCL: Deviation due to the transmission line (generally due to the transceivers) All the deviations of the system should be added and compared to the SCI clock tolerance: DTRA + DQUANT + DREC + DTCL < 3.75%
11.5.4.10 Noise Error Causes See also description of Noise error in Section 11.5.4.3. Start bit The noise flag (NF) is set during start bit reception if one of the following conditions occurs: 1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a "1". 2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a "1". Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set. Data Bits The noise flag (NF) is set during normal data bit reception if the following condition occurs: - During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set.
Figure 56. Bit Sampling in Reception Mode RDI LINE sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
6/16 7/16 One bit time 7/16
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 11.5.5 Low Power Modes Mode WAIT Description No effect on SCI. SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Interrupt Event
Enable Exit Event Control from Flag Bit Wait TIE TCIE RIE ILIE PIE Yes Yes Yes Yes Yes Yes
Exit from Halt No No No No No No
HALT
11.5.6 Interrupts The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control Bit is set and the inter-
Transmit Data Register TDRE Empty Transmission ComTC plete Received Data Ready RDRF to be Read Overrun Error Detected OR Idle Line Detected IDLE Parity Error PE
rupt mask in the CC register is reset (RIM instruction).
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 11.5.7 Register Description Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line ocSTATUS REGISTER (SCISR) curs). Read Only Reset Value: 1100 0000 (C0h) Bit 3 = OR Overrun error. 7 0 This bit is set by hardware when the word currently being received in the shift register is ready to be TDRE TC RDRF IDLE OR NF FE PE transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an Bit 7 = TDRE Transmit data register empty. access to the SCISR register followed by a read to This bit is set by hardware when the content of the the SCIDR register). TDR register has been transferred into the shift 0: No Overrun error register. An interrupt is generated if the TIE bit=1 1: Overrun error is detected in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register folNote: When this bit is set RDR register content will lowed by a write to the SCIDR register). not be lost but the shift register will be overwritten. 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Bit 2 = NF Noise flag. Note: Data will not be transferred to the shift regThis bit is set by hardware when noise is detected ister unless the TDRE bit is cleared. on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). Bit 6 = TC Transmission complete. 0: No noise is detected This bit is set by hardware when transmission of a 1: Noise is detected frame containing Data is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it apcleared by a software sequence (an access to the pears at the same time as the RDRF bit which itSCISR register followed by a write to the SCIDR self generates an interrupt. register). 0: Transmission is not complete 1: Transmission is complete Bit 1 = FE Framing error. This bit is set by hardware when a de-synchronizaNote: TC is not set after the transmission of a Pretion, excessive noise or a break character is deamble or a Break. tected. It is cleared by a software sequence (an access to the SCISR register followed by a read to Bit 5 = RDRF Received data ready flag. the SCIDR register). This bit is set by hardware when the content of the 0: No Framing error is detected RDR register has been transferred to the SCIDR 1: Framing error or break character is detected register. An interrupt is generated if RIE=1 in the Note: This bit does not generate interrupt as it apSCICR2 register. It is cleared by a software sepears at the same time as the RDRF bit which itquence (an access to the SCISR register followed self generates an interrupt. If the word currently by a read to the SCIDR register). being transferred causes both frame error and 0: Data is not received overrun error, it will be transferred and only the OR 1: Received data is ready to be read bit will be set. Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected Bit 0 = PE Parity error. This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register. 0: No parity error 1: Parity error
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) CONTROL REGISTER 1 (SCICR1) Read/Write Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is Reset Value: x000 0000 (x0h) set or cleared by software. 0: Idle Line 7 0 1: Address Mark
R8 T8 SCID M WAKE PCE PS PIE
Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception).
Bit 2 = PCE Parity control enable. This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled Bit 1 = PS Parity selection. This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity Bit 0 = PIE Parity interrupt enable. This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) CONTROL REGISTER 2 (SCICR2) Notes: Read/Write - During transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble (idle line) Reset Value: 0000 0000 (00h) after the current word. 7 0 - When TE is set there is a 1 bit-time delay before the transmission starts. TIE TCIE RIE ILIE TE RE RWU SBK Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 2 = RE Receiver enable. 1: An SCI interrupt is generated whenever This bit enables the receiver. It is set and cleared TDRE=1 in the SCISR register by software. 0: Receiver is disabled Bit 6 = TCIE Transmission complete interrupt ena1: Receiver is enabled and begins searching for a ble start bit This bit is set and cleared by software. 0: Interrupt is inhibited Bit 1 = RWU Receiver wake-up. 1: An SCI interrupt is generated whenever TC=1 in This bit determines if the SCI is in mute mode or the SCISR register not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is Bit 5 = RIE Receiver interrupt enable. recognized. This bit is set and cleared by software. 0: Receiver in Active mode 0: Interrupt is inhibited 1: Receiver in Mute mode 1: An SCI interrupt is generated whenever OR=1 Note: Before selecting Mute mode (setting the or RDRF=1 in the SCISR register RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with Bit 4 = ILIE Idle line interrupt enable. wakeup by idle line detection. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 0 = SBK Send break. 1: An SCI interrupt is generated whenever IDLE=1 This bit set is used to send break characters. It is in the SCISR register. set and cleared by software. Bit 3 = TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to "1" and then to "0", the transmitter will send a BREAK word at the end of the current word.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
DR7 DR6 DR5 DR4 DR3 DR2 DR1
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR dividing factor 1 2 4 8 16 32 64 128 SCT2 0 0 0 0 1 1 1 1 SCT1 0 0 1 1 0 0 1 1 SCT0 0 1 0 1 0 1 0 1
0
DR0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 53). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 53). BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h)
7
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.
RR Dividing factor 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1
0
SCR1 SCR0
Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges:
PR Prescaling factor 1 3 4 13 SCP1 0 0 1 1 SCP0 0 1 0 1
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate division factor for the receive circuit.
7 0
EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate division factor for the transmit circuit.
7
ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2
0
ETPR ETPR 1 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 55) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. Table 19. Baudrate Selection
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 55) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset.
Conditions Symbol Parameter fCPU Accuracy vs. Standard Prescaler Conventional Mode TR (or RR)=128, PR=13 TR (or RR)= 32, PR=13 TR (or RR)= 16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 16, PR= 3 TR (or RR)= 2, PR=13 TR (or RR)= 1, PR=13 Extended Mode ETPR (or ERPR) = 35, TR (or RR)= 1, PR=1 Standard Baud Rate Unit
~0.16% fTx fRx Communication frequency 8MHz
300 ~300.48 1200 ~1201.92 2400 ~2403.84 4800 ~4807.69 9600 ~9615.38 10400 ~10416.67 19200 ~19230.77 38400 ~38461.54 14400 ~14285.71
Hz
~0.79%
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Table 20. SCI Register Map and Reset Values
Address (Hex.) 50 51 52 53 54 55 56 Register Name SCISR Reset Value SCIDR Reset Value SCIBRR Reset Value SCICR1 Reset Value SCICR2 Reset Value SCIERPR Reset Value SCIETPR Reset Value 7 TDRE 1 DR7 x SCP1 0 R8 x TIE 0 ERPR7 0 ETPR7 0 6 TC 1 DR6 x SCP0 0 T8 0 TCIE 0 ERPR6 0 ETPR6 0 5 RDRF 0 DR5 x SCT2 0 SCID 0 RIE 0 ERPR5 0 ETPR5 0 4 IDLE 0 DR4 x SCT1 0 M 0 ILIE 0 ERPR4 0 ETPR4 0 3 OR 0 DR3 x SCT0 0 WAKE 0 TE 0 ERPR3 0 ETPR3 0 2 NF 0 DR2 x SCR2 0 PCE 0 RE 0 ERPR2 0 ETPR2 0 1 FE 0 DR1 x SCR1 0 PS 0 RWU 0 ERPR1 0 ETPR1 0 0 PE 0 DR0 x SCR0 0 PIE 0 SBK 0 ERPR0 0 ETPR0 0
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11.6 I2C BUS INTERFACE (I2C) 11.6.1 Introduction The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400kHz). 11.6.2 Main Features 2 Parallel-bus/I C protocol converter Multi-master capability 7-bit/10-bit Addressing SMBus V1.1 Compliant Transmitter/Receiver flag End-of-byte transmission flag Transfer problem detection I2C Master Features: Clock generation 2 I C bus busy flag Arbitration Lost Flag End of byte transmission flag Transmitter/Receiver Flag Start bit detection flag Start and Stop generation I2C Slave Features: Stop bit detection 2 I C bus busy flag Detection of misplaced start or stop condition 2 Programmable I C Address detection Transfer problem detection End-of-byte transmission flag Transmitter/Receiver flag 11.6.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format Figure 57. I2C BUS Protocol SDA MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION ACK and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a Fast I2C bus. This selection is made by software. Mode Selection The interface can operate in the four following modes: - Slave transmitter/receiver - Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability. Communication Flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 57.
VR02119B
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I2C BUS INTERFACE (Cont'd) Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (up to 100KHz) and Fast I2C (up to 400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. Figure 58. I2C Interface Block Diagram
The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) STATUS REGISTER 2 (SR2) CONTROL LOGIC
INTERRUPT
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I2C BUS INTERFACE (Cont'd) 11.6.4 Functional Description Refer to the CR, SR1 and SR2 registers in Section 11.6.7. for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. 11.6.4.1 Slave Mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set. Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: - Acknowledge pulse if the ACK bit is set. - EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 59 Transfer sequencing EV1). Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - Acknowledge pulse if the ACK bit is set - EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV2). Slave Transmitter Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV3). When the acknowledge pulse is received: - The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: - EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 59 Transfer sequencing EV4). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. Note: In case of errors, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software.
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I2C INTERFACE (Cont'd) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus Compatibility ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus adressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave Driver For ST7 I2C Peripheral. 11.6.4.2 Master Mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent: - The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see Figure 59 Transfer sequencing EV5). Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the following event: - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV9).
Then the second address byte is sent by the interface. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 59 Transfer sequencing EV6). Next the master must enter Receiver or Transmitter mode. Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master Receiver Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - Acknowledge pulse if the ACK bit is set - EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV7). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
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I2C BUS INTERFACE (Cont'd) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: - EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note that BERR will not be set if an error is detected during the first or second pulse of each 9bit transaction: Single Master Mode If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle
of communication gives the possibility to reinitiate transmission. Multimaster Mode Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I2C master is on the first or second pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. - ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible 0 bits transmitted last. It is then necessary to release both lines by software.
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I2C BUS INTERFACE (Cont'd) Figure 59. Transfer Sequencing 7-bit Slave receiver:
S Address A EV1 Data1 A EV2 Data2 A EV2 ..... DataN A EV2 P EV4
7-bit Slave transmitter:
S Address A EV1 EV3 Data1 A EV3 Data2 A EV3 ..... DataN NA EV3-1 P EV4
7-bit Master receiver:
S EV5 Address A EV6 Data1 A EV7 Data2 A EV7 ..... DataN NA EV7 P
7-bit Master transmitter:
S EV5 Address A EV6 EV8 Data1 A EV8 Data2 A EV8 ..... DataN A EV8 P
10-bit Slave receiver:
S Header A Address A EV1 Data1 A EV2 ..... DataN A EV2 P EV4
10-bit Slave transmitter:
Sr Header A EV1 EV3 Data1 A .... DataN EV3 . A EV3-1 P EV4
10-bit Master transmitter
S EV5 Header A EV9 Address A EV6 EV8 Data1 A EV8 ..... DataN A EV8 P
10-bit Master receiver:
Sr EV5 Header A EV6 Data1 A EV7 ..... DataN A EV7 P
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading SR1 register. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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I2C BUS INTERFACE (Cont'd) 11.6.5 Low Power Modes
Mode
2
Description No effect on I C interface. I2C interrupts cause the device to exit from WAIT mode. I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
WAIT HALT
11.6.6 Interrupts Figure 60. Event Flags and Interrupt Generation
ADD10 BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT
EVF
* * EVF can also be set by EV6 or an error from the SR2 register.
Event Flag ADD10 BTF ADSEL SB AF STOPF ARLO BERR Enable Control Bit Exit from Wait Yes Yes Yes Yes Yes Yes Yes Yes Exit from Halt No No No No No No No No
Interrupt Event 10-bit Address Sent Event (Master mode) End of Byte Transfer Event Address Matched Event (Slave mode) Start Bit Generation Event (Master mode) Acknowledge Failure Event Stop Detection Event (Slave mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event
ITE
Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).
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I2C BUS INTERFACE (Cont'd) 11.6.7 Register Description I2C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 PE ENGC START ACK STOP 0 ITE
- In slave mode: 0: No start generation 1: Start generation when the bus is free Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). - In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. - In slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 60 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 59) is detected.
Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: - When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 - When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. - To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 = ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Note: In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can only receive data. It will not transmit data to the master. Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). - In master mode: 0: No start generation 1: Repeated start generation
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I2C BUS INTERFACE (Cont'd) I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h)
7 EVF ADD10 TRA BUSY BTF ADSL M/SL 0 SB
1: Data byte transmitted Bit 4 = BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs. 0: No communication on the bus 1: Communication ongoing on the bus Note: - The BUSY flag is NOT updated when the interface is disabled (PE=0). This can have consequences when operating in Multimaster mode; i.e. a second active I2C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. A software workaround consists of checking that the I2C is not busy before enabling the I2C Multimaster cell. Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). - Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 59). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. - Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched
Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 59. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: - BTF=1 (Byte received or transmitted) - ADSL=1 (Address matched in Slave mode while ACK=1) - SB=1 (Start condition generated in Master mode) - AF=1 (No acknowledge received after byte transmission) - STOPF=1 (Stop condition detected in Slave mode) - ARLO=1 (Arbitration lost in Master mode) - BERR=1 (Bus error, misplaced Start or Stop condition detected) - ADD10=1 (Master has sent header byte) - Address byte successfully transmitted in Master mode. Bit 6 = ADD10 10-bit addressing in Master mode. This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0). 0: No ADD10 event occurred. 1: Master has sent first address byte (header) Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1)
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I2C BUS INTERFACE (Cont'd) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated I2C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h)
7 0 0 0 AF 0 STOPF ARLO BERR GCAL
The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected Bit 2 = ARLO Arbitration lost. This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Note: - In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. Bit 1 = BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Note: - If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus
Bit 7:5 = Reserved. Forced to 0 by hardware. Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time. 0: No acknowledge failure 1: Acknowledge failure Note: - When an AF event occurs, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. Bit 3 = STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
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I2C BUS INTERFACE (Cont'd) I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h)
7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 0 CC0
I2C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode Bit 6:0 = CC[6:0] 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not cleared when the interface is disabled (PE=0). Refer to the Electrical Characteristics section for the table of values. Note: The programmed FSCL assumes no load on SCL and SDA lines.
Bit 7:0 = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. - Transmitter mode: Byte transmission start automatically when the software writes in the DR register. - Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register.
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I2C BUS INTERFACE (Cont'd) I2C OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h)
7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 0 ADD0
I2C OWN ADDRESS REGISTER (OAR2) Read / Write Reset Value: 0100 0000 (40h)
7 FR1 FR0 0 0 0 ADD9 ADD8 0 0
7-bit Addressing Mode Bit 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 Address direction bit. This bit is don't care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. 10-bit Addressing Mode Bit 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0).
Bit 7:6 = FR[1:0] Frequency bits. These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I2C specified delays select the value corresponding to the microcontroller frequency FCPU.
fCPU < 6 MHz 6 to 8 MHz FR1 0 0 FR0 0 1
Bit 5:3 = Reserved Bit 2:1 = ADD[9:8] Interface address. These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0). Bit 0 = Reserved.
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IC BUS INTERFACE (Cont'd) Table 21. I2C Register Map and Reset Values
Address (Hex.) 0028h 0029h 002Ah 02Bh 02Ch 002Dh 002Eh Register Label I2CCR Reset Value I2CSR1 Reset Value I2CSR2 Reset Value I2CCCR Reset Value I2COAR1 Reset Value I2COAR2 Reset Value I2CDR Reset Value 7 6 5 PE 0 TRA 0 0 CC5 0 ADD5 0 0 0 4 ENGC 0 BUSY 0 AF 0 CC4 0 ADD4 0 0 0 3 START 0 BTF 0 STOPF 0 CC3 0 ADD3 0 0 0 2 ACK 0 ADSL 0 ARLO 0 CC2 0 ADD2 0 ADD9 0 0 1 STOP 0 M/SL 0 BERR 0 CC1 0 ADD1 0 ADD8 0 0 0 ITE 0 SB 0 GCAL 0 CC0 0 ADD0 0 0 LSB 0
0 EVF 0 0 FM/SM 0 ADD7 0 FR1 0 MSB 0
0 ADD10 0 0 CC6 0 ADD6 0 FR0 1 0
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11.7 10-BIT A/D CONVERTER (ADC) 11.7.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has 6 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from 6 different sources. The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register. 11.7.2 Main Features 10-bit conversion 6 channels with multiplexed input Linear successive approximation Figure 61. ADC Block Diagram fCPU fADC Data register (DR) which contains the results Conversion complete status flag On/off bit (to reduce consumption) The block diagram is shown in Figure 61.

11.7.3 Functional Description 11.7.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.
fCPU, fCPU/2, fCPU/4
EOC SPEED ADON SLOW
0
CH2
CH1
CH0
ADCCSR
3
AIN0
AIN1
ANALOG MUX
AINx
ANALOG TO DIGITAL CONVERTER
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
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10-BIT A/D CONVERTER (ADC) (Cont'd) 11.7.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.7.3.3 A/D Conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: - Select the CH[2:0] bits to assign the analog channel to convert. ADC Conversion mode In the ADCCSR register: - Set the SPEED or the SLOW bits - Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: - The EOC bit is set by hardware. - The result is in the ADCDR registers. A read to the ADCDRH or a write to any bit of the ADCCSR resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRL. This locks the ADCDRH until it is read. 3. Read ADCDRH. This clears EOC automatically. To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automatically. 11.7.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed.
HALT
11.7.5 Interrupts None.
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10-BIT A/D CONVERTER (ADC) (Cont'd) 11.7.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h)
7
EOC SPEED ADON SLOW 0 CH2 CH1
Bit 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
Channel Pin 0
CH0
CH2 0 0 0 0 1 1
CH1 0 0 1 1 0 0
CH0 0 1 0 1 0 1
Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register or writing to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED A/D clock selection This bit is set and cleared by software. Table 22. A/D Clock Selection (See Note 1)
fADC Frequency fCPU (See Note 2) fCPU/2 fCPU/4
1)The 2)
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5
DATA REGISTER (ADCDRH) Read Only Reset Value: 0000 0000 (00h)
7
D9 D8 D7 D6 D5 D4 D3
0
D2
SLOW 0 1 0 1
SPEED 1 1 0 0
Bit 7:0 = D[9:2] MSB of Analog Converted Value DATA REGISTER (ADCDRL) Read Only Reset Value: 0000 0000 (00h)
7
0 0 0 0 0 0 D1
SPEED and SLOW bits must be updated before setting the ADON bit. Use this setting only if fCPU 4 MHz
0
D0
Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: Disable ADC and stop conversion 1: Enable ADC and start conversion Bit 4 = SLOW A/D Clock Selection This bit is set and cleared by software. It works together with the SPEED bit. Refer to Table 22.
Bit 7:2 = Reserved. Forced by hardware to 0. Bit 1:0 = D[1:0] LSB of Analog Converted Value
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10-BIT A/D CONVERTER (ADC) (Cont'd) Table 23. ADC Register Map and Reset Values
Address (Hex.) 006Fh 0070h 0071h Register Label ADCDRL Reset Value ADCDRH Reset Value ADCCSR Reset Value 7 6 5 4 3 2 1 D1 0 D3 0 CH1 0 0 D0 0 D2 0 CH0 0
0 D9 0 EOC 0
0 D8 0 SPEED 0
0 D7 0 ADON 0
0 D6 0 SLOW 0
0 D5 0 0
0 D4 0 CH2 0
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12 INSTRUCTION SET
12.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do Table 24. CPU Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination
Pointer Address (Hex.)
Pointer Size (Hex.)
Length (Bytes) +0 +1
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word
+1 +2 +0 +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
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INSTRUCTION SET OVERVIEW (Cont'd) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
12.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
12.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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INSTRUCTION SET OVERVIEW (Cont'd) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 25. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function
12.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Available Relative Direct/Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset is following the opcode. Relative (Indirect) The offset is defined in memory, which address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear
Function
Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine
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INSTRUCTION SET OVERVIEW (Cont'd) 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 12.2.1 Illegal Opcode Reset In order to provide enhanced robustness to the device against unexpected behaviour, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset.
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. INT pin = 1 Jump if ext. INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I1:0 = 11 Jump if I1:0 <> 11 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) jrf * (ext. INT pin high) (ext. INT pin low) H=1? H=0? I1:0 = 11 ? I1:0 <> 11 ? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Pop CC, A, X, PC inc X jp [TBL.w] reg, M tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 1 I1 H 0 I0 N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst Src M M M M I1 H H H I0 N N N N N Z Z Z Z Z C C C
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Substract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I1:0 = 10 (level 0) C <= A <= C C => A => C S = Max allowed A=A-M-C C=1 I1:0 = 11 (level 3) C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A=A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt 1 1 1 0 N Z reg, M reg, M reg, M reg, M A reg, M M 1 1 N N 0 N N N N Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 1 0 N N Z Z C C A=A+M pop reg pop CC push Y C=0 A reg CC M M M M reg, CC 0 I1 H I0 N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src I1 H I0 N Z C
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13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 13.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD=5V (for the 3VVDD5.5V voltage range) and VDD=2.7V (for the 2.7VVDD3V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 13.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 62. Figure 62. Pin loading conditions 13.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 63. Figure 63. Pin input voltage
ST7 PIN
VIN
ST7 PIN
CL
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13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi13.2.1 Voltage Characteristics
Symbol VDD - VSS VIN VESD(HBM) VESD(MM) Supply voltage Input voltage on any pin
1) & 2)
tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Ratings
Maximum value 6.5 VSS-0.3 to VDD+0.3
Unit V
Electrostatic discharge voltage (Human Body Model) Electrostatic discharge voltage (Machine Model)
see Section 13.7.3 on page 142
13.2.2 Current Characteristics
Symbol IVDD IVSS IIO Ratings Total current into VDD power lines (source) Total current out of VSS ground lines (sink)
3) 3)
Maximum value 100 150 25 50 - 25 +5 5 5 5 20
5) & 6)
Unit mA
Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on Flash device pins PB0 and PB1 IINJ(PIN) 2) & 4) Injected current on RESET pin Injected current on OSC1 and OSC2 pins Injected current on any other pin IINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5)
13.2.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Value -65 to +150 Unit C
Maximum junction temperature (see Section Figure 104. "Low Profile Fine Pitch Ball Grid Array Package" on page 160)
Notes: 1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10k for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. For reset pin, please refer to Figure 91 and Figure 92. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN127/172
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13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions
TA = -40 to +85C unless otherwise specified.
Symbol VDD fOSC Parameter Supply voltage Conditions fOSC = 8 MHz. max. fOSC = 16 MHz. max. Min 2.7 3.3 up to 8 Max 5.5 5.5 Unit V MHz
External clock frequency on OSC1 VDD3.3V pin VDD2.7V
up to 16
Figure 64. fOSC Maximum Operating Frequency Versus VDD Supply Voltage
fOSC [MHz] FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA)
16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 8 4 1 0 2.0 2.7 3.3 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE [V]
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OPERATING CONDITIONS (Cont'd) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) TA = -40 to +85C unless otherwise specified
Symbol VIT+(LVD) Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) LVD voltage threshold hysteresis VDD rise time rate 1)2)3) Filtered glitch delay on VDD 1) Conditions High Threshold Med. Threshold Low Threshold High Threshold Med. Threshold Low Threshold VIT+(LVD)-VIT-(LVD) Flash ROM Not detected by the LVD 20s/V 20s/V Min 4.0 3.55 1) 2.95 1) 3.75 3.3 2.75
1)
Typ 4.2 3.75 3.15 4.0 3.55 3.0 200
Max 4.5 4.0 3.35 4.251) 3.751) 3.151) 20ms/V
Unit
V
VIT-(LVD) Vhys(LVD) VtPOR tg(VDD)
mV
40
ns
Notes: 1. Data based on characterization results, not tested in production. 2. When VtPOR is faster than 100 s/V, the Reset signal is released after a delay of max. 42s after VDD crosses the VIT+(LVD) threshold. 3. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 91 on page 151 and note 6. .
Figure 65. LVD Startup Behaviour
5V VIT+ LVD RESET
VD
D
2V Reset state not defined in this area t
Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state. However, in some devices, the reset signal may be undefined until VDD is approximately 2V. As a consequence, the I/Os may toggle when VDD is below this voltage. Because Flash write access is impossible below this voltage, the Flash memory contents will not be corrupted.
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OPERATING CONDITIONS (Cont'd) 13.3.3 Auxiliary Voltage Detector (AVD) Thresholds TA = -40 to +85C unless otherwise specified
Symbol VIT+(AVD) Parameter 10 AVDF flag toggle threshold (VDD rise) 01 AVDF flag toggle threshold (VDD fall) AVD voltage threshold hysteresis Voltage drop between AVD flag set and LVD reset activated Conditions VD level = Low in option byte VD level = Med. in option byte VD level = High in option byte VD level = Low in option byte VD level = Med. in option byte VD level = High in option byte VIT+(AVD)-VIT-(AVD) VIT-(AVD)-VIT-(LVD) Min 4.4 3.91) 3.4 1) 4.15 3.75 3.1
1)
Typ 4.6 4.2 3.6 4.4 3.95 3.4 250 450
Max 4.9 4.4 3.8 4.651) 4.21) 3.61)
Unit
V
VIT-(AVD) Vhys(AVD) VIT-
mV
1. Data based on characterization results, not tested in production.
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13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
Symbol IDD(Ta) Parameter Supply current variation vs. temperature Conditions Constant VDD and fCPU Max 10 Unit %
13.4.1 RUN, SLOW, WAIT and SLOW WAIT Modes TA = -40 to +85C unless otherwise specified
Symbol Parameter Supply current in RUN mode 2) (see Figure 66) Supply current in SLOW mode 3) (see Figure 67) Supply current in WAIT mode 2) (see Figure 68) Supply current in SLOW WAIT mode 3) (see Figure 69) Conditions VDD=5.5V,fOSC=16MHz, fCPU=8MHz VDD=2.7V, fOSC=8MHz, fCPU=4MHz VDD=5.5V, fOSC=16MHz, fCPU=500kHz VDD=2.7V, fOSC=8MHz, fCPU=250kHz VDD=5.5V,fOSC=16MHz, fCPU=8MHz VDD=2.7V, fOSC=8MHz, fCPU=4MHz VDD=5.5V, fOSC=16MHz, fCPU=500kHz VDD=2.7V, fOSC=8MHz, fCPU=250kHz FLASH Typ 7.2 3.5 0.7 0.38 3.6 1.8 0.45 0.25 Max 111) 5.254) 1.21) 0.64) 5.551) 34) 11) 0.54) ROM Typ 5.0 1.2 0.5 0.13 2.3 0.5 0.33 0.08 Max TBD Unit Unit
TBD mA TBD
IDD
TBD
Notes: 1. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Program executed from RAM, CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled. 3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled. 4. Data based on characterization results, not tested in production.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) Figure 66. Typical IDD in RUN at TA=25C
10 9 8 7 Idd (mA) 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 Vdd (V) 5 5.5 6 6.5 Fosc=16MHz Fosc=8MHz Fosc=4MHz Fosc=2MHz
Figure 68. Typical IDD in WAIT at TA=25C
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 2.5 Fosc=16MHz Fosc=8MHz Fosc=4MHz Fosc=2MHz
Idd(mA)
3
3.5
4
4.5 Vdd(V)
5
5.5
6
6.5
Figure 67. Typical IDD in SLOW at TA=25C
0.8 0.7 0.6 Idd(mA) 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6 6.5 Fosc=16MHz Fosc=8MHz Fosc=4MHz Fosc=2MHz
Figure 69. Typ. IDD in SLOW-WAIT at TA=25C
0.6 0.5 0.4 Idd(mA) 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6 6.5 Fosc=16MHz Fosc=8MHz Fosc=4MHz Fosc=2MHz
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 13.4.2 HALT and ACTIVE-HALT Modes
Symbol Parameter Supply current in HALT mode 1) IDD Supply current in ACTIVE-HALT mode 2) 500 VDD=5.5V VDD=2.7V Conditions -40CTA+85C -40CTA+85C Typ <1 <1 Max 10 6 No max. guaranteed A Unit
13.4.3 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock
Symbol Parameter
source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Conditions Typ 900 see Section 13.5.3 on page 136 VDD=5V HALT mode 100 100 A Max Unit
IDD(RCINT) Supply current of internal RC oscillator IDD(RES) IDD(PLL) IDD(LVD) Supply current of resonator oscillator 3) & 4) PLL supply current LVD supply current
Notes: 1. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Data based on characterisation results, not tested in production. All I/O pins in output mode with a static value at VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the total current consumption of the device, add the clock source consumption (Section 13.5.3 and Section 13.5.4). 3. Data based on characterization results done with the external components specified in Section 13.5.3 and Section 13.5.4, not tested in production. 4. As the oscillator is based on a current source, the consumption does not depend on the voltage.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 13.4.4 On-chip peripherals
Symbol IDD(TIM) IDD(SPI) IDD(SCI) IDD(I2C) IDD(ADC) Parameter 16-bit Timer supply current 1) SPI supply current 2) SCI supply current 3) I2C supply current 4) ADC supply current when converting 5) Conditions fCPU=4MHz fCPU=8MHz fCPU=4MHz fCPU=8MHz fCPU=4MHz fCPU=8MHz fCPU=4MHz fCPU=8MHz fADC=4MHz VDD=3.0V VDD=5.0V VDD=3.0V VDD=5.0V VDD=3.0V VDD=5.0V VDD=3.0V VDD=5.0V VDD=3.0V VDD=5.0V Typ 200 300 200 250 350 650 350 500 500 600 A Unit
Notes: 1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/2) and timer counter stopped (only TIMD bit set). Data valid for one timer. 2. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master communication at maximum speed (data sent equal to FFh).This measurement includes the pad toggling consumption. 3. Data based on a differential IDD measurement between SCI running at maximum speed configuration (500 kbaud, continuous transmission of AA +RE enabled and SCI off. This measurement includes the pad toggling consumption. 4. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent I2C master communication at 300kHz (data sent equal to AAh). This measurement includes the pad toggling consumption (4.7kOhm external pull-up on clock and data lines). 5. Data based on a differential IDD measurement between reset configuration (ADC off) and continuous A/D conversion (fADC=4MHz).
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13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
2)
Conditions fCPU=8MHz fCPU=8MHz
Min 2 250 10 1.25
Typ 1) 3 375
Max 12 1500 22 2.75
Unit tCPU ns tCPU s
13.5.2 External Clock Source
Symbol VOSC1H VOSC1L tw(OSC1H) tw(OSC1L) tr(OSC1) tf(OSC1) IL Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 3) OSC1 rise or fall time 3) OSCx Input leakage current VSSVINVDD see Figure 70 Conditions Min 0.7xVDD VSS 15 ns 15 1 A Typ Max VDD 0.3xVDD Unit V
Figure 70. Typical Application with an External Clock Source
90% VOSC1H 10%
VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
OSC2
Not connected internally fOSC
EXTERNAL CLOCK SOURCE
OSC1
IL ST72XXX
Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production.
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as
Symbol Parameter
close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Conditions Min 0.032 1 >2 >4 >8 20 60 38 32 10 10 Typ 2.5 80 160 310 610 Max 0.1 2 4 8 16 40 100 100 47 47 30 Max 5 150 250 460 900 Unit
fOSC
Oscillator Frequency 1)
VLP : Very Low power oscillator LP: Low power oscillator MP: Medium power oscillator MS: Medium speed oscillator HS: High speed oscillator VLP oscillator LP oscillator MP oscillator MS oscillator HS oscillator Conditions VDD=5V VIN=VSS VLP oscillator LP oscillator MP oscillator MS oscillator HS oscillator
MHz
RF CL1 CL2
Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS) RS=200 RS=200 RS=200 RS=100
k
pF
Symbol
Parameter
Unit
i2
OSC2 driving current
A
Figure 71. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH INTEGRATED CAPACITORS
i2
fOSC OSC1
CL1
RESONATOR CL2
RF
OSC2
RD
ST72XXX Notes: 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details.
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CLOCK AND TIMING CHARACTERISTICS (Cont'd)
fOSC (MHz) 2 Murata 4 8 16 Typical Ceramic Resonators Reference2) CSTCC2M00G56A-R0 CSTCR4M00G55B-R0 CSTCE8M00G55A-R0 CSTCE16M0G53A-R0 Recommended OSCRNGE Option bit Configuration MP Mode3) MS Mode HS Mode HS Mode
Supplier
Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer. 2. SMD = [-R0: Plastic tape package ( =180mm), -B0: Bulk] LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk] 3. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (>0.8V) For more information on these resonators, please consult www.murata.com
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CLOCK CHARACTERISTICS (Cont'd) 13.5.4 RC Oscillators The ST7 internal clock can be supplied with an internal RC oscillator.
Symbol fOSC (RCINT) Parameter Internal RC oscillator frequency See Figure 73 Conditions TA=25C, VDD=5V Min 2 Typ 3.5 Max 6 Unit MHz
Figure 72. Typical Application with RC oscillator
ST72XXX
INTERNAL RC VDD
Current copy
CIN
RIN
VREF
+ -
fOSC
Voltage generator
CEX discharge
Figure 73. Typical fOSC(RCINT) vs VDD
4.5 4 3.5 3 F(MHz) 2.5 2 1.5 1 0.5 0 2.35 5 Vdd(V) 5.5 T=25C T=130C T=-45C
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CLOCK CHARACTERISTICS (Cont'd) 13.5.5 PLL Characteristics
Symbol VDD(PLL) fOSC fCPU/fCPU Parameter PLL Operating Range PLL input frequency range Instantaneous PLL jitter 1) fOSC = 4 MHz. fOSC = 2 MHz. Conditions TA 0 to 70C TA -40 to +85C Min 3.5 4.5 2 1.0 2.5 Typ Max 5.5 5.5 4 2.5 4.0 Unit V MHz % %
Note: 1. Data characterized but not tested.
Figure 74. PLL Jitter vs. Signal frequency1
0.8 0.7 0.6 +/-Jitter (%) 0.5 0.4 0.3 0.2 0.1 0 2000 1000 500 250 125 Application Signal Frequency (KHz) PLL ON PLL OFF
The user must take the PLL jitter into account in the application (for example in serial communication or sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the PLL jitter. Figure 74 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequencies of less than 125KHz, the jitter is negligible.
Note 1: Measurement conditions: fCPU = 4MHz, TA= 25C
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13.6 MEMORY CHARACTERISTICS 13.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode
1)
Conditions HALT mode (or RESET)
Min 1.6
Typ
Max
Unit V
13.6.2 XFlash Program Memory
Symbol VDD tprog tRET NRW Parameter Operating voltage for Flash write/ erase Programming time for 1~32 bytes 2) TA=-40 to +85C TA=+25C Programming time for 1.5kBytes Data retention 4) Write erase cycles TA=+55C3) TA=+25C Read / Write / Erase modes fCPU = 8MHz, VDD = 5.5V No Read/No Write Mode Power down mode / HALT 20 10 2.63) 100 0.15) Conditions Min 2.7 5 0.24 Typ Max 5.5 10 0.48 years kcycles mA A A Unit V ms
IDD
Supply current
0
Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production. 5. Data based on characterization results, not tested in production.
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13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 13.7.1.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical applicaSymbol VFESD VFFTB Parameter
tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Conditions Level/ Class 2B 2B
Voltage limits to be applied on any I/O pin to induce a VDD=5V, TA=+25C, fOSC=8MHz functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be applied V =5V, TA=+25C, fOSC=8MHz through 100pF on VDD and VDD pins to induce a func- DD conforms to IEC 1000-4-4 tional disturbance
Figure 75. EMC Recommended power supply connection 1)
ST72XXX 10F 0.1F
ST7 DIGITAL NOISE FILTERING
VDD
VSS
POWER SUPPLY SOURCE
VDD
1. The suggested 10F and 0.1F decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in AN1709.
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EMC CHARACTERISTICS (Cont'd) 13.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin.
Symbol Parameter Conditions Monitored Frequency Band 0.1MHz to 30MHz SEMI Peak level 30MHz to 130MHz VDD=5V, TA=+25C, conforming to SAE J 1752/3 130MHz to 1GHz SAE EMI Level Max vs. [fOSC/fCPU] 8/4MHz 10 13 16 2.5 16/8MHz 13 24 31 4 dBV Unit
13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
13.7.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.
Absolute Maximum Ratings
Symbol VESD(HBM) VESD(MM) Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) TA=+25C TA=+25C Conditions Maximum value 1) Unit 2000 V 200
Notes: 1. Data based on characterization results, not tested in production.
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EMC CHARACTERISTICS (Cont'd) 13.7.3.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Electrical Sensitivities
Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.
Conditions TA=+25C TA=+85C VDD=5.5V, fOSC=4MHz, TA=+25C
Class 1) A A A
Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
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13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics TA = -40 to +85C unless otherwise specified
Symbol VIL VIH Vhys Parameter Input low level voltage1) Input high level voltage1) Schmitt trigger voltage hysteresis 1) Conditions Min Vss - 0.3 0.7xVDD 400 +4 4 25 1
3)
Typ
Max 0.3xVDD VDD + 0.3
Unit V mV
Injected current on Flash device IINJ(PIN)2) pins PB0 and PB1 Injected Current on other I/O pins Total injected current (sum of all I/O VDD=5V IINJ(PIN)2) and control pins) IL IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Input leakage current Static current consumption Weak pull-up equivalent resistor 4) I/O pin capacitance Output high to low level fall time External interrupt pulse time5) CL=50pF Output low to high level rise time 1) Between 10% and 90% 1
1)
mA
VSSVINVDD Floating input mode VIN=VSS 400 50 1701) 85 190 5 25 25 VDD=5V VDD=3V
A k pF ns tCPU
250 2301)
Notes: 1. Data based on characterization results, not tested in production. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINFigure 76. Two typical Applications with unused I/O Pin configured as input
VDD 10k
ST7XXX
10k UNUSED I/O PORT UNUSED I/O PORT
ST7XXX
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 77. Typical IPU vs. VDD with VIN=VSS
120 100 80 60 40 20 0
Ipu(uA) at Vin=Vss
T=25C T=-45C T=90C
2 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V)
Figure 78. Typical VIL
2.5 2 Vil(V) 1.5 1 0.5 0 2 3 4 Vdd(V)
Figure 79. Typical VIH
T=25C T=-45C
5
6
4 Vih(V) 3 2 1 2 3 4 Vdd(V) 5 6
T=25C T=-45C
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I/O PORT PIN CHARACTERISTICS (Cont'd) 13.8.2 Output Driving Current TA = -40 to +85C unless otherwise specified
Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time VDD=5V Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time Conditions IIO=+5mA IIO=+2mA IIO=+20mA, IIO=+8mA IIO=-5mA, IIO=-2mA IIO=+2mA VDD=3.3V IIO=+8mA IIO=-2mA IIO=+2mA VDD=2.7V IIO=+8mA IIO=-2mA VDD-0.9 TA85C VDD-0.8 0.7 0.7 VDD-1.6 VDD-0.8 0.6 0.6 V Min Max 1.2 0.5 1.3 0.75 Unit
VOL 1)
VOH 2)
Output low level voltage for a standard I/O pin when 8 pins are sunk at same time VOL 1)3) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time VOH 2)3) Output high level voltage for an I/O pin when 4 pins are sourced at same time Output low level voltage for a standard I/O pin when 8 pins are sunk at same time Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time
VOL
1)3)
VOH 2)3)
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH. 3. Not tested in production, based on characterization results.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 80. Typ. VOL at VDD=5V (standard) Figure 82. Typ. VOL at VDD=2.7V (standard)
0.5
T=25C T=90C T=-45C
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1
0.5 0.4
Vol(V) at Vdd= 5V
T=25C T=90C T=-45C Vol (V) 4 5 Iio(mA) 6 7 8 9 10
0.4 0.3 0.3 0.2 0.2 0.1 0.1
2
3
0.0 0 1 2
Iio(mA)
Figure 81. Typ. VOL at VDD=3V (high-sink)
1 0.9 0.8 0.7 Vol(V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 Iol(mA) 10 12 14 16
Figure 83. Typ. VOL at VDD=5V (high-sink)
0.8 0.7 Vol(V) at Vdd=5V T=25C T=90C T=-45C
T=25C T=90C T=-45C
0.6 0.5 0.4 0.3 0.2 0.1 0
0 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 20 Iio(mA)
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 84. Typ. VOH at VDD=2.7V
3 2.5 2 Voh(V) 1.5 1 0.5 0 0 0.5 1 Iio(mA) 1.5 2 T=90C T=-45C
Voh(V)
Figure 86. Typ. VOH at VDD=3V
3.5 3 2.5
T=25C
2 1.5 1 0.5 0 0
T=25C T=90C T=-45C
1 Iio(mA)
2
3
Figure 85. Typ. VOH at VDD=4V
4.5 4 3.5 3 Voh(V) 2.5 2 1.5 1 0.5 0 0 1 2 Iio(mA) 3 4 5
Figure 87. Typ. VOH at VDD=5V
6 5
T=25C
Voh(V)
4 3 2 1 0 0 1 2 Iio(mA) 3 4 5 T=25C T=90C T=-45C
T=90C T=-45C
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 88. Typical VOL vs. VDD on standard I/O port (Ports B and C)
1.0
0.6
T=25C T=90C T=-45C
VOL(V) at Iio= 5mA
T=25C T=90C T=-45C
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
VOL(V) at Iio= 2mA
0.5 0.4 0.3 0.2 0.1 0.0 2.5 3 3.5 4 5
5.5
6
0.0 3.5 4 5 5.5 6
Vdd (V)
Vdd (V)
Figure 89. Typical VOL vs. VDD on high sink I/O port (Port A)
0.6
1.2
T=25C
0.5
T=25C T=90C T=-45C
T=90C T=-45C
1.0
VOL(V) at Iio= 20mA
VOL(V) at Iio= 8mA
0.4
0.8 0.6 0.4 0.2 0.0
0.3
0.2
0.1
0.0 2.4 3 3.5 4 5 5.5 6
3
3.5
4
5
5.5
6
Vdd (V)
Vdd (V)
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13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin TA = -40 to +85C unless otherwise specified
Symbol VIL VIH Vhys VOL RON Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis1) Output low level voltage 2) Pull-up equivalent resistor VDD=5V VDD=5V VDD=3V Internal reset sources 20 200 IIO=+5mA IIO=+2mA 20 Conditions Min Vss - 0.3 0.7xVDD 2.5 0.68 0.28 40 85 30 0.95 0.45 80 Typ Max 0.3xVDD VDD + 0.3 Unit V V V k s s ns
tw(RSTL)out Generated reset pulse duration th(RSTL)in tg(RSTL)in External reset pulse hold time 3) Filtered glitch duration
Figure 90. Typical IPU on RESET pin
250
T=25C T=90C T=-45C
Ipu(uA) at Vin=Vss
200 150 100 50 0 2.4
3
4
5
5.5
6
Vdd (V)
Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored.
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CONTROL PIN CHARACTERISTICS (Cont'd) Figure 91. RESET pin protection when LVD is enabled.1)2)3)4)
VDD
ST72XXX
Required
EXTERNAL RESET
0.01F
Optional (note 3)
RON
Filter
INTERNAL RESET
1M
PULSE GENERATOR
WATCHDOG ILLEGAL OPCODE 5) LVD RESET
Figure 92. RESET pin protection when LVD is disabled.1)
Recommended for EMC
VDD VDD
VDD
ST72XXX
USER EXTERNAL RESET CIRCUIT
0.01F
4.7k
RON
Filter
INTERNAL RESET
0.01F
PULSE GENERATOR
WATCHDOG ILLEGAL OPCODE 5)
Required Note 1: - The reset network protects the device against parasitic resets. - The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). - Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 13.9.1 on page 150. Otherwise the reset will not be taken into account internally. - Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in Section 13.2.2 on page 127. Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line. Note 3: In case a capacitive power supply is used, it is recommended to connect a 1M pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5A to the power consumption of the MCU). Note 4: Tips when using the LVD: - 1. Check that all recommendations related to the reset circuit have been applied (see notes above). - 2. Check that the power supply is properly decoupled (100nF + 10F close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M pull-down on the RESET pin. - 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5F to 20F capacitor." Note 5: Please refer to "Illegal Opcode Reset" on page 123 for more details on illegal opcode reset conditions.
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13.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). 13.10.1 16-Bit Timer TA = -40 to +85C unless otherwise specified
Symbol Parameter Conditions Min 1 2 fCPU=8MHz 250 0 0 fCPU/4 fCPU/4 16 Typ Max Unit tCPU tCPU ns MHz MHz bit tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fEXT fPWM Timer external clock frequency PWM repetition rate
ResPWM PWM resolution
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13.11 COMMUNICATION INTERFACE CHARACTERISTICS 13.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter Master SPI clock frequency fCPU=8MHz Slave fCPU=8MHz SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge) 0 0.25 0.25 tCPU
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Conditions Min fCPU/128 0.0625 0 Max fCPU/4 2 fCPU/2 4 Unit
MHz
see I/O port pin description 120 120 100 90 100 100 100 100 0 120 240 120
ns
Figure 93. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
see note 2
see note 2
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 94. SPI Slave Timing Diagram with CPHA=11)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
MISO OUTPUT
see note 2
HZ
MSB OUT
BIT6 OUT
see note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 95. SPI Master Timing Diagram 1)
SS INPUT tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT
see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) 13.11.2 I2C - Inter IC Control Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) Cb SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 Parameter
(SDAI and SCLI). Refer to Table 26 for the speed conditions. The ST7 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table.
Standard mode I2C Min 1) 4.7 4.0 250 0
3)
Fast mode I2C5) Min 1) 1.3 0.6 100 0 2) 900 3) 300 300 Max 1)
Max 1)
Unit s
1000 300
20+0.1Cb 20+0.1Cb 0.6 0.6 0.6 1.3
ns
s s s 400 pF
tw(STO:STA) STOP to START condition time (bus free)
Figure 96. Typical Application with I2C Bus and Timing Diagram 4)
VDD 4.7k I C BUS
2
VDD 4.7k 100 100 SDAI SCLI
ST72XXX
REPEATED START START
tsu(STA)
SDA
tw(STO:STA)
START
tf(SDA)
SCL
tr(SDA)
tsu(SDA)
th(SDA)
STOP
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Notes: 1. Data based on standard I2C protocol requirement, not tested in production. 2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 5. At 4MHz fCPU, max.I2C speed (400kHz) is not achievable. In this case, max. I2C speed will be approximately 260KHz.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) The following table gives the values to be written in the I2CCCR register to obtain the required I2C SCL line frequency. Table 26. SCL Frequency Table
I2CCCR Value fSCL (kHz) 400 300 200 100 50 20 fCPU=4 MHz. VDD = 3.3 V RP=3.3k RP=4.7k NA NA NA NA 83h 84h 10h 10h 24h 24h 5Fh 5Fh VDD = 5 V RP=3.3k RP=4.7k NA NA NA NA 83h 84h 10h 10h 24h 24h 5Fh 5Fh fCPU=8 MHz. VDD = 3.3 V RP=3.3k RP=4.7k 83h NA 85h 85h 8Ah 89h 24h 23h 4Ch 4Ch FFh FFh VDD = 5 V RP=3.3k RP=4.7k 83h 83h 85h 85h 8Ah 8Ah 24h 23h 4Ch 4Ch FFh FFh
Legend: RP = External pull-up resistance fSCL = I2C speed NA = Not achievable Note: - For speeds around 200 kHz, achieved speed can have 5% tolerance - For other speed ranges, achieved speed can have 2% tolerance The above variations depend on the accuracy of the external components used.
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13.12 10-BIT ADC CHARACTERISTICS VDD= 2.7 to 5.5V, TA = -40C to 85C, unless otherwise specified
Symbol fADC VAIN CADC Parameter ADC clock frequency Conversion voltage range Internal sample and hold capacitor FLASH, fADC=4MHz tCONV Conversion time ROM, fADC=4MHz RAIN CAIN fAIN External input impedance External capacitor on analog input Variation frequency of analog input signal Conditions Min 0.5 VSS 6 28 112 3.5 14 see Figure 97 and Figure 981)2)3) Typ Max 4 VDD Unit MHz V pF s 1/fADC s 1/fADC k pF Hz
Figure 97. RAIN max. vs fADC with CAIN=0pF2)
45 40
Figure 98. Recommended CAIN/RAIN values3)
1000
Cain 10 nF
4 MHz
Max. R AIN (Kohm)
35 30 25 20 15 10 5 0 0 10 30
Max. R AIN (Kohm)
2 MHz 1 MHz
100
Cain 22 nF Cain 47 nF
10
1
0.1
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Figure 99. Analog Input equivalent circuit
VDD VT 0.6V RAIN VAIN CAIN VT 0.6V IL 1A AINx
ST72XXX
2k(max)
10-Bit A/D Conversion CADC 6pF
Notes: 1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 2. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and decreased to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies 4MHz.
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ADC CHARACTERISTICS (Cont'd) 13.12.0.1 General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise generating CMOS logic signals. - Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted.
ADC Accuracy with fCPU=8 MHz, fADC=4 MHz RAIN< 10k, VDD= 4.5V to 5.5V
Symbol |ET| |EO| |EG| |ED| |EL| Parameter Total unadjusted error 1) Offset error Gain
1)
Conditions
FLASH Typ 4 1 1 1.5 3
2)
ROM Typ
2)
Max 6 5 4.5 4.5 4.5
Max TBD TBD TBD TBD TBD
Unit
TBD TBD TBD TBD TBD
Error 1)
LSB
Differential linearity error1) Integral linearity error 1)
Figure 100. ADC Accuracy Characteristics
Digital Result ADCDR 1023 1022 1021 1LSB IDEAL V -V DD SS = -------------------------------
EG
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
1024
(2) ET 7 6 5 4 3 2 1 0 VSS 1 2 3 4 1 LSBIDEAL EO EL ED (3) (1)
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Vin (LSBIDEAL) 5 6 7 1021 1022 1023 1024 VDD
Notes: 1. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the analog input pins significantly reduces the accuracy of the conversion being performed on another analog input. For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 4 LSB for each 10K increase of the external analog source impedance. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 13.8 does not affect the ADC accuracy. 2. Refer to "Typical values" on page 126 for more information on typical ADC accuracy values.
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14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA Figure 101. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
mm Min 3.56 0.51 3.05 0.36 0.76 0.20 27.43 7.62 8.89 1.78 10.16 12.70 1.40 2.54 3.05 Number of Pins N 32 3.56 0.46 1.02 0.25 Typ 3.76 Max Min 0.020 4.57 0.120 0.140 0.180 0.58 0.014 0.018 0.023 1.40 0.030 0.040 0.055 0.36 0.008 0.010 0.014 28.45 1.080 1.100 1.120 9.40 0.300 0.350 0.370 0.070 0.400 0.500 0.055 inches Typ Max 5.08 0.140 0.148 0.200
Dim.
E eC
A
A2 A
A1 A2 b
E1 C eA eB
A1
L
b1 C D E E1 e eA eB eC L
b2 D
b
e
9.91 10.41 11.05 0.390 0.410 0.435
3.81 0.100 0.120 0.150
Figure 102. Figure 103. 28-Pin Plastic Small Outline Package, 300-mil Width
Dim.
D
L
mm Min 2.35 0.10 0.33 0.23 17.70 7.40 1.27 10.00 0.25 0 0.40 10.65 0.394 0.75 0.010 8 0 1.27 0.016 Typ Max Min 2.65 0.093 0.30 0.004 0.51 0.013 0.32 0.009 18.10 0.697 7.60 0.291
inches Typ Max 0.104 0.012 0.020 0.013 0.713 0.299 0.050 0.419 0.030 8 0.050
h x 45x
A
C
A1
A a
A1 B C D E e H h
B
e
EH
L N
Number of Pins 28
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Figure 104. Low Profile Fine Pitch Ball Grid Array Package
SEATING PLANE C A2 A ddd C
Dim A A2 b D D1 E E1 E1 E e f ddd
mm Min 1.210 1.120 Typ Max Min 0.011 1.700 0.048
inches Typ Max 0.067 0.044
A1
A1 0.270 D D1 e f
0.450 0.500 0.550 0.018 0.020 0.022 5.750 6.000 6.150 0.226 0.236 0.242 4.000 4.000 0.157 0.157 5.750 6.000 6.150 0.226 0.236 0.242 0.720 0.800 0.880 0.028 0.031 0.035 0.850 1.000 1.150 0.033 0.039 0.045 0.120 0.005
A1 CORNER INDEX AREA (SEE NOTE 3)
b (36 BALLS)
BOTTOM VIEW
14.2 THERMAL CHARACTERISTICS
Symbol Ratings Package thermal resistance (junction to ambient) SDIP32 SO28 LFBGA 6x6 (on multilayer PCB) LFBGA 6x6 (on single-layer PCB) Power dissipation 1) Maximum junction temperature
2)
e
f
Value 60 75 56 72 500 150
Unit
RthJA
C/W
PD TJmax
mW C
Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
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14.3 LEAD-FREE PACKAGE INFORMATION STMicroelectronics is fully committed to Environment protection and sustainable development and started in 1997 a volontary program for removing polluting and hazardous substances from all devices. In 2000, a strategic program, named ECOPACK(R), has been officially launched to develop and implement solutions leading to environment friendly packaging and ban progressively Pb and other heavy metals from our manufacturing lines. Please refer to application notes AN2033, AN2034, AN2035 and AN2036 for further information.
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15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (ROM/FASTROM). ST7226x devices are ROM versions. ST72P26x devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory-programmed XFlash devices. ST72F26x XFlash devices are shipped to customers with a default program memory content (FFh). The option bytes are programmed to enable the internal RC oscillator. The ROM/FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the ROM/FASTROM devices are factoryconfigured. 15.1 OPTION BYTES The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). USER OPTION BYTE 0 OPT 7 = WDG HALT Watchdog reset on HALT This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode OPT 6 = WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software)
USER OPTION BYTE 0 7 0 7
OPT 5:4 = VD[1:0] Voltage detection selection These option bits enable the voltage detection block (LVD and AVD) with a selected threshold of the LVD and AVD.
Configuration LVD Off Lowest Voltage Threshold (3.05V) Medium Voltage Threshold (3.6V) Highest Voltage Threshold (4.1V) VD1 1 1 0 0 VD0 1 0 1 0
OPT 3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 according to the following table.
Sector 0 Size 0.5k 1k 2 4k
1)
SEC1 0 0 1 1
SEC0 0 1 0 1
Note 1: 4k available on FASTROM devices only. OPT 1 = FMP_R Read-out protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first, and the device can be reprogrammed. Refer to Section 4.5 and the ST7 Flash Programming Reference Manual for more details. 0: Read-out protection off 1: Read-out protection on
USER OPTION BYTE 1 0
OSC OSC OSC OSC OSC PLL WDG WDG SEC SEC FMP FMP VD1 VD0 EXTIT Res. TYPE TYPE RNGE RNGE RNGE HALT SW 1 0 R W OFF 0 1 2 0 1 Default Value 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1
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ST72260Gx, ST72262Gx, ST72264Gx
DEVICE CONFIGURATION (Cont'd) OPT 0 = FMP_W FLASH write protection This option indicates if the FLASH program memory is write protected. Warning: When this option is selected, the program memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on USER OPTION BYTE 1 OPT 7 = EXTIT Port C External Interrupt Configuration. This option bit allows the Port C external interrupt mapping to be configured as ei0 or ei1. Table 27. External Interrupt Configuration
ei0 ei1 PB[7:0] Ports PC[5:0] Ports PB[7:0] Ports EXTIT option bit 1 0
OPT 3:1 = OSCRNGE[2:0] Oscillator Range selection These option bits select the oscillator range.
OSC RNGE2 1 0 0 0 0 OSC RNGE1 x 0 0 1 1 OSC RNGE0 x 0 1 0 1
Typ. Freq. Range VLP 32~100kHz LP MP MS HS 1~2MHz 2~4MHz 4~8MHz 8~16MHz
PA[7:0] Ports PA[7:0] Ports PC[5:0] Ports
OPT 6 = Reserved, must be kept at default value. OPT 5:4 = OSCTYPE[1:0] Oscillator Type selection These option bits select the Oscillator Type.
Clock Source Resonator Oscillator Reserved Internal RC Oscillator External Source OSCTYPE1 OSCTYPE0 0 0 1 1 0 1 0 1
OPT 0 = PLL PLL selection This option bit selects the PLL which allows multiplication by two of the oscillator frequency. The PLL must not be used with the internal RC oscillator. It is guaranteed only with a fOSC input frequency between 2 and 4MHz. 0: PLL x2 enabled 1: PLL x2 disabled CAUTION: the PLL can be enabled only if the "OSC RANGE" (OPT3:1) bits are configured to "MP - 2~4MHz". Otherwise, the device functionality is not guaranteed.
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ST72260Gx, ST72262Gx, ST72264Gx
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM/FASTROM contents and the list of the selected options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Table 28. Supported Part Numbers
Part Number ST72F264G1B6 ST72F264G1M6 ST72F262G1B6 ST72F262G1M6 ST72F264G2B6 ST72F264G2M6 ST72F264G2H1 ST72F264G2H6E ST72F262G2B6 ST72F262G2M6 ST72F262G1B6 ST72F262G1M6 ST72F260G1B6 ST72F260G1M6 ST72P264G2B6/xxx ST72P264G2M6/xxx ST72P264G2H1/xxx ST72P262G2B6/xxx ST72P262G2M6/xxx ST72P262G1B6/xxx ST72P262G1M6/xxx ST72P260G1B6/xxx ST72P260G1M6/xxx ST72264G2B6/xxx ST72264G2M6/xxx ST72262G2B6/xxx ST72262G2M6/xxx ST72262G1B6/xxx ST72262G1M6/xxx ST72260G1B6/xxx ST72260G1M6/xxx 4K ROM 256 8K ROM 256 -40C +85C 4K FASTROM 256 -40C +85C 8K FASTROM 256 -40C +85C 0C +70C 4K FLASH 256 -40C +85C 8K FLASH 256 0C +70C -40C +85C 4K FLASH 256 -40C +85C Program Memory (Bytes) RAM (Bytes) Temp. Range Package SDIP32 SO28 SDIP32 SO28 SDIP32 SO28 LFBGA lead-free LFBGA SDIP32 SO28 SDIP32 SO28 SDIP32 SO28 SDIP32 SO28 LFBGA SDIP32 SO28 SDIP32 SO28 SDIP32 SO28 SDIP32 SO28 SDIP32 SO28 SDIP32 SO28 SDIP32 SO28
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TRANSFER OF CUSTOMER CODE (Cont'd)
................................................................................ ................................................................................ ................................................................................ Contact ................................................................................ Phone No ................................................................................ Reference /ROM or FASTROM Code* ROM or FASTROM code is assigned by STMicroelectronics. Code must be sent in .S19 format. .Hex extension cannot be processed. Customer Address
ST72264 ROM/FASTROM MICROCONTROLLER OPTION LIST (Last update: 15 January 2004)
Device Type/Memory Size/Package (check only one option): ---------------------------- | -------------------------------------------- | ---------------------------------------------------------------8K 4K ROM DEVICE: ---------------------------- | -------------------------------------------- | ---------------------------------------------------------------SO28: | [ ]ST72264G2 [ ]ST72262G2 | [ ]ST72264G1 [ ]ST72262G1 [ ]ST72260G1 SDIP32: | [ ]ST72264G2 [ ]ST72262G2 | [ ]ST72264G1 [ ]ST72262G1 [ ]ST72260G1 --------------------------- | -------------------------------------------- | ---------------------------------------------------------------8K 4K FASTROM DEVICE: | ---------------------------- -------------------------------------------- | ---------------------------------------------------------------SO28: | [ ]ST72P264G2 [ ]ST72P262G2 | [ ]ST72P264G1 [ ]ST72P262G1 [ ]ST72P260G1 SDIP32: | [ ]ST72P264G2 [ ]ST72P262G2 | [ ]ST72P264G1 [ ]ST72P262G1 [ ]ST72P260G1 BGA6x6: | [ ]ST72P264G2 | ---------------------------- | ------------------------------------------- | ---------------------------------------------------------------DIE FORM: [ ] 8K [ ] 4K ---------------------------- | -------------------------------------------- | ---------------------------------------------------------------Conditioning (check only one option, do not specify for DIP package): SO package: [ ] Tape & Reel [ ] Tube Die form: [ ] Tape & Reel [ ] Inked wafer [ ] Sawn wafer on sticky foil
Special Marking [ ] No [ ] Yes Authorized characters are letters, digits `.', `-', `/' and spaces only. Maximum character count: SO28 (13 char. max): _ _ _ _ _ _ _ _ _ _ _ _ _ SDIP32 (15 char. max): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ BGA6x6 (7 char. max): _ _ _ _ _ _ _ Temperature Range: Packaged form: [ ] 0C to + 70C [ ] - 10C to + 85C (except BGA) [ ] - 40C to + 85C (except BGA) Die form: [ ] Tested at 25C only [ ] No Reset [ ] Hardware Activation [ ] Enabled: [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold Sector 0 Size: [ ] 0.5K [ ] 1K [ ] 2K [ ] 4K (FASTROM only) Readout Protection: [ ] Disabled [ ] Enabled Flash Write Protection: [ ] Disabled [ ] Enabled (FASTROM only) External Interrupt: [ ] Port A&C on ei0 interrupt vector, Port B on ei1 (PA&C_PB) [ ] Port A on ei0 interrupt vector, Port B&C on ei1 (PA_PB&C) Clock Source Selection: [ ] Resonator: [ ] VLP: Very Low power resonator (32 to 100 kHz) [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) 1) [ ] Internal RC Oscillator [ ] External Clock 1 [ ] Disabled [ ] Enabled PLL : Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes: ................................................................................ Signature: ................................................................................ Watchdog Reset on Halt: Watchdog Selection: VD Reset [ ] Reset [ ] Software Activation [ ] Disabled
Note 1: Use of the PLL with the internal RC oscillator is not supported. Important note: Not all configurations are available. See Table 28 on page 164 for the list of supported part numbers.
Please download the latest version of this option list from: http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
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15.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtained from the STMicroelectronics Internet site: http//www.st.com. Tools from these manufacturers include C compliers, evaluation tools, emulators and programmers. Emulators Two types of emulators are available from ST for the ST72260/262/264 family: ST7 DVP3 entry-level emulator offers a flexible and modular debugging and programming solution. ST7 EMU3 high-end emulator is delivered with everything (probes, TEB, adapters etc.) needed to start emulating the ST72260/262/264. To configure it to emulate other ST7 subfamily devices, the active probe for the ST7EMU3 can be changed and the ST7EMU3 probe is designed for easy interchange of TEBs (Target Emulation Board). See Table 29. In-circuit Debugging Kit Three configurations are available from ST: ST7F264-IND/USB: Low-cost In-Circuit Debugging kit from Softec Microsystems. Table 29. STMicroelectronics Development Tools
Emulation Supported Products ST7 DVP3 Series Emulator ST7226xGx ST7MDT10DVP31) Connection kit ST7MDT10-32/DVP ST7 EMU3 series Emulator ST7MDT10EMU31) Active Probe & ICC Socket Board T.E.B. ST7MDT10-TEB ST7SB10-26x2) Programming
Includes STX-InDART/USB board (USB port) and one specific evaluation board for ST72264 (package SDIP32) ST7F264-INDART: Low-cost In-Circuit Debugging kit from Softec Microsystems Includes STX-InDART/USB board (parallel port) and one specific evaluation board for ST72264 (package SDIP32) STxF-INDART/USB Flash Programming tools ST7-STICK ST7 In-circuit Communication Kit, a complete software/hardware package for programming ST7 Flash devices. It connects to a host PC parallel port and to the target board or socket board via ST7 ICC connector. ICC Socket Boards provide an easy to use and flexible means of programming ST7 Flash devices. They can be connected to any tool that supports the ST7 ICC interface, such as ST7 EMU3, ST7-DVP3, inDART, ST7-STICK, or many third-party development tools. Evaluation boards One evaluation tool is available from ST: ST7FOPTIONS-EVAL: ST7 Clock Security System evaluation board
Notes: 1. BGA adapter not available for ST7MDT10-DVP3 and ST7MDT10-EMU3 . 2. Add suffix /EU, /UK, /US for the power supply of your region. 15.3.1 Related Documentation AN 978: Key features of the STVD7 ST7 Visual Debug Package AN 983: Key Features of the Cosmic ST7 C-Compiler Package AN 988: Getting started with ST7 Assembly Tool chain AN 989: Getting started with ST7 Hiware C Toolchain AN1604: How to use ST7MDT1-TRAIN with ST72F264
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15.3.2 PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 30. Suggested List of SDIP32 Socket Types
Package / Probe SDIP32 EMU PROBE TEXTOOL Adaptor / Socket Reference 232-1291-00 Same Footprint X Socket Type Textool
Table 31. Suggested List of SO28 Socket Types
Package / Probe SO28 EMU PROBE YAMAICHI Adaptor / Socket Reference IC51-0282-334-1 X Same Footprint Socket Type Clamshell SMD to SDIP
Adapter from SO28 to SDIP32 footprint (delivered with emulator)
Table 32. Suggested LFBGA Socket Type
Package LFBGA 6 X6 Socket Reference
ENPLAS OTB-36(144)-0.8-04
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16 KNOWN LIMITATIONS
16.1 ALL FLASH AND ROM DEVICES 16.1.1 16-bit timer PWM Mode In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC12R register.In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on the OLVL1 and OLVL2 settings. 16.1.2 Clearing active interrupts outside interrupt routine When an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the CC register may be corrupted. Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: - The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine - The interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine - The interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following sequence: Perform SIM and RIM operation before and after resetting an active interrupt request Ex: SIM reset flag or interrupt mask RIM Nested interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: - The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine - The interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine with higher or identical priority level - The interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following sequence: PUSH CC SIM reset flag or interrupt mask POP CC 16.1.3 I2C Multimaster In multimaster configurations, if the ST7 I2C receives a START condition from another I2C master after the START bit is set in the I2CCR register and before the START condition is generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In this case, the ST7 master will receive a NACK from the other device. On reception of the NACK, ST7 can send a re-start and Slave address to re-initiate communication 16.1.4 Functional EMS The functional EMS (Electro Magnetic Susceptibility) severity level/behaviour class is 2B as defined in application note AN1709. Special care should be taken when designing the PCB layout and firmware (refer to application notes AN898, AN901 and AN1015) in sensitive applications (that use switches for instance). For more information refer to application note AN1637. 16.2 FLASH DEVICES ONLY 16.2.1 Execution of BTJX instruction When testing the address $FF with the "BTJT" or "BTJF" instructions, the CPU may perform an incorrect operation when the relative jump is negative and performs an address page change. To avoid this issue, including when using a C compiler, it is recommended to never use address $00FF as a variable (using the linker parameter for example).
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16.2.2 I/O Port B and C configuration When using an external quartz crystal or ceramic resonator, the fOSC2 clock may be disturbed because the device goes into reserved mode controlled by Port B and C. This happens with either one of the following configurations: PB1=0, PC2=1, PB3=0 while PLL option is both disabled and PC4 is toggling PB1=0, PC2=1, PB3=0, PC4=1 while PLL option is enabled This is detailed in the following table: PLL PB1 PC2 PB3 PC4 Tog OFF 0 1 0 glin g ON 0 1 0 1 Clock Disturbance Max. 2 clock cycles lost at each rising or falling edge of PC4 Max. 1 clock cycle lost out of every 16
As a consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. Workaround: To avoid this occurring, it is recommended to connect one of these pins to GND (PC2 or PC4) or VDD (PB1 or PB3). 16.2.3 16-bit Timer PWM mode After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 16.2.4 SPI Multimaster Mode Multi master mode is not supported. 16.2.5 Internal RC oscillator with LVD If the LVD is disabled, the internal RC oscillator clock source cannot be used. In ICP mode, new flash devices must be programmed with an external clock connected to the OSC1 pin or using a crystal or ceramic resonator. In the STVP7 programming tool software, select the "OPTIONS DISABLED" mode. 16.2.6 External clock with PLL The PLL option is not supported for use with external clock source. 16.2.7 Halt mode power consumption with ADC on If the A/D converter is being used when Halt mode is entered, the power consumption in Halt Mode may exceed the maximum specified in the datasheet.
Workaround Switch off the ADC by software (ADON=0) before executing a HALT instruction. 16.2.8 Active Halt wake-up by external interrupt External interrupts are not able to wake-up the MCU from Active Halt mode. The MCU can only exit from Active Halt mode by means of an MCC/ RTC interrupt or a reset. Workaround Use WAIT mode if external interrupt capability is required in low power mode. 16.2.9 SCI Wrong Break duration Description A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: - 20 bits instead of 10 bits if M=0 - 22 bits instead of 11 bits if M=1. In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than expected. Occurrence The occurrence of the problem is random and proportional to the baudrate. With a transmit frequency of 19200 baud (fCPU=8MHz and SCIBRR=0xC9), the wrong break duration occurrence is around 1%. Workaround If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. This can be ensured by temporarily disabling interrupts. The exact sequence is: - Disable interrupts - Reset and Set TE (IDLE request) - Set and Reset SBK (Break Request) - Re-enable interrupts 16.2.10 A/D converter accuracy for first conversion When the ADC is enabled after being powered down (for example when waking up from HALT, ACTIVE-HALT or setting the ADON bit in the ADCCSR register), the first conversion (8-bit or 10-
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bit) accuracy does not meet the accuracy specified in the data sheet. Workaround In order to have the accuracy specified in the datasheet, the first conversion after a ADC switch-on has to be ignored. 16.2.11 Negative injection impact on ADC accuracy Injecting a negative current on an analog input pins significantly reduces the accuracy of the AD Converter. Whenever necessary, the negative injection should be prevented by the addition of a Schottky diode between the concerned I/Os and ground.
Injecting a negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to ADC channel in use. 16.2.12 ADC conversion spurious results Spurious conversions occur with a rate lower than 50 per million. Such conversions happen when the measured voltage is just between 2 consecutive digital values. Workaround A software filter should be implemented to remove erratic conversion results whenever they may cause unwanted consequences.
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17 REVISION HISTORY
Table 33. Revision History
Date Rev. Main changes
February-2005
Added "SMBus V1.1 Compliant" for IC on page 1 Added one note in Section 6.4.1 on page 24 Added SMBus compatibility information in Section 11.6 on page 103 and at the end of Section 11.6.4.1 on page 105 Changed note 1 in Section 13.2 on page 127 Added note 3 in Section 13.3.2 on page 129 Changed IS value and note 3 in Section 13.8.1 on page 144 2.0 Added note in Figure 76 on page 144 Changed Figure 91 on page 151 and notes and added note 4 to Figure 92 on page 151 Added "LEAD-FREE PACKAGE INFORMATION" on page 161 Added ST72F264G2H6E in Table 28, "Supported Part Numbers," on page 164 Changed Section 15.3 on page 166 Changed "ST72264 ROM/FASTROM MICROCONTROLLER OPTION LIST (Last update: 15 January 2004)" on page 165 Added -40C to +85C operating range in "Device Summary" on first page for LFBGA package (lead-free LFBGA package) Added illegal opcode reset on page 1, and in Section 12.2.1 on page 123 Changed notes under Figure 91 on page 151 Changed VtPOR max. for ROM and note 3. Removed VHYS min and maxin Section 13.3.2 on page 129 Changed Reset VIL/VIH in Section 13.9 on page 150 Added ROM current consumption in Section 13.4.1 on page 131 Added Active HALT min.in Section 13.4.2 on page 133 Removed note under table in Section 13.7.2 on page 142 Changed note on PB0/PB1 to apply to Flash only in Section 13.2 on page 127 and Section 13.8 on page 144 Added VDD range for ADC operation, fADC min , conversion time and accuracy for ROM devices in Section 13.12 on page 157. Added 16-bit timer PWM Section 16.2.3 on page 169 Added SCI wrong break duration Section 16.2.9 on page 169 Moved errata sheet to Section 16 on page 168 and updated section for ROM and Flash devices
01-Jun-05
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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